Driver and electronic device

Patent metadata

Field	Value
Publication number	US-2016163285-A1
Application number	US-201514954025-A
Country	US
Kind code	A1
Filing date	Nov 30, 2015
Priority date	Dec 5, 2014
Publication date	Jun 9, 2016
Grant date	—

Abstract

A driver and an electronic device include a capacitor driving circuit and a capacitor circuit having a plurality of capacitors provided between a plurality of capacitor driving nodes and a data voltage output terminal. The capacitor driving circuit has a plurality of driving units that output capacitor driving voltages, and in the case where a capacitance of one of the plurality of capacitors is the highest, after a driving unit that drives that capacitor has outputted a capacitor driving voltage, the next driving unit outputs the next capacitor driving voltage.

First claim

What is claimed is:

1 . A driver comprising:
a capacitor driving circuit that outputs first to nth capacitor driving voltages (where n is a natural number of 2 or more) corresponding to tone data to first to nth capacitor driving nodes; and a capacitor circuit including first to nth capacitors provided between the first to nth capacitor driving nodes and a data voltage output terminal, wherein the capacitor driving circuit includes first to nth driving units that output the first to nth capacitor driving voltages; and in the case where a capacitance of the nth capacitor of the first to nth capacitors is the highest, an n−1th driving unit of the first to nth driving units outputs an n−1th capacitor driving voltage of the first to nth capacitor driving voltages after the nth driving unit among the first to nth driving units has outputted the nth capacitor driving voltage.

2 . The driver according to claim 1 ,
wherein in the case where a capacitance of an ith capacitor (where i is a natural number, with 1≦i≦n) of the first to nth capacitors is greater than a capacitance of a jth capacitor (where j is a natural number, with j<i and 1≦j≦n), a jth driving unit of the first to nth driving units outputs a jth capacitor driving voltage of the first to nth capacitor driving voltages after an ith driving unit of the first to nth driving units has outputted an ith capacitor driving voltage of the first to nth capacitor driving voltages.

3 . The driver according to claim 2 ,
wherein in the case where a delay time of a signal in the ith driving unit is represented by tdi and a delay time of a signal in the jth driving unit is represented by tdj, tdi>tdj; and a delay time of a jth input signal inputted into the jth driving unit relative to an ith input signal inputted into the ith driving unit is greater than tdi−tdj.

4 . The driver according to claim 1 , further comprising:
a signal output circuit that outputs first to nth input signals to the first to nth driving units, wherein the signal output circuit outputs the first to nth input signals to the first to nth driving units having delayed an n−1th input signal of the first to nth input signals more than an nth input signal of the first to nth input signals.

5 . The driver according to claim 2 , further comprising:
a signal output circuit that outputs first to nth input signals to the first to nth driving units, wherein the signal output circuit outputs the first to nth input signals to the first to nth driving units having delayed a jth input signal (where j is a natural number, with j<i and 1≦j≦n) of the first to nth input signals more than an ith input signal (where i is a natural number, with 1≦i≦n) of the first to nth input signals.

6 . The driver according to claim 1 ,
wherein in the case where driving capabilities of the first to nth driving units are represented by D 1 to Dn and capacitances of the first to nth capacitors are represented by C 1 to Cn, the driving capability Dn of the nth driving unit is set so that Dn/Cn<D 1 /C 1 .

7 . The driver according to claim 1 ,
wherein at least the nth driving unit of the first to nth driving units is a driving unit whose driving capability is variable.

8 . The driver according to claim 1 , further comprising:
a variable capacitance circuit provided between the data voltage output terminal and a reference voltage node, wherein a capacitance of the variable capacitance circuit is set so that a capacitance obtained by adding a capacitance of the variable capacitance circuit and an electro-optical panel-side capacitance is in a prescribed capacitance ratio relationship with a capacitance of the capacitor circuit.

9 . An electronic device comprising the driver according to claim 1 .

10 . An electronic device comprising the driver according to claim 2 .

11 . An electronic device comprising the driver according to claim 3 .

12 . An electronic device comprising the driver according to claim 4 .

13 . An electronic device comprising the driver according to claim 5 .

14 . An electronic device comprising the driver according to claim 6 .

15 . An electronic device comprising the driver according to claim 7 .

16 . An electronic device comprising the driver according to claim 8 .

Assignees

• Seiko Epson Corp

Inventors

• Morita Akira

Classifications

• G09G3/3688 Primary

  suitable for active matrices only · CPC title

• G09G2310/027

  Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters · CPC title

• G09G2310/0297

  Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title

• H03M1/0863

  of switching transients, e.g. glitches · CPC title

• G09G3/20

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title