Sata receiver equalization margin determination/setting method and apparatus

Patent metadata

Field	Value
Publication number	US-2016162379-A1
Application number	US-201414564869-A
Country	US
Kind code	A1
Filing date	Dec 9, 2014
Priority date	Dec 9, 2014
Publication date	Jun 9, 2016
Grant date	—

Abstract

Apparatuses, methods and storage medium associated with automatic SATA receiver equalization margin determination and setting, are disclosed. In embodiments, an apparatus may comprise a BIOS configured to determine, during POST, whether a device is attached to one of the SATA ports, and on determination that a device is attached to one of the SATA ports, further determine whether a receiver equalization margin has been set for the device. Additionally, the BIOS may be configured to perform a DTLE training to dynamically determine and set the receiver equalization margin for the device, on determination that a receiver equalization margin has not been set for the device. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1 . An apparatus for computing, comprising:
one or more processors; one or more serial advance technology attachment (SATA) ports; and a basic input-output system (BIOS) to be operated by the one or more processors to:
determine, during a power on self test (POST) phase of boot up of the apparatus, whether a device is attached to a first of the one or more SATA ports;
on determination that a device is attached to the first SATA port, further determine whether a receiver equalization margin has been set for the device; and
on determination that a receiver equalization margin has not been set for the device, perform a discrete time linear equalization (DTLE) training to dynamically determine and set the receiver equalization margin for the device.

2 . The apparatus of claim 1 , wherein the BIOS, on entry into the POST phase is to enable the one or more SATA ports, including, for each SATA port, determination of whether it is necessary to down speed the SATA port, and on determination it is necessary, down speed the SATA port.

3 . The apparatus of claim 2 , wherein the BIOS is to determine whether it is necessary to down speed the SATA port via determination of whether DTLE support is to be provided for the SATA port, and whether the SATA port is of a particular generation of SATA ports; and wherein the BIOS is to further determine whether it is necessary to down speed the SATA port via determination of whether the SATA port is an external SATA (eSATA) port.

4 . The apparatus of claim 1 , wherein to determine whether a receiver equalization margin has been set for the device attached to the first SATA port, the BIOS is to:
get prior device information associated with the first SATA port, including a device serial number and the DTLE value previously associated with the first SATA port; identify and obtain serial number for the device currently attached to the first SATA port; determine whether the first SATA port is of a particular generation; and on determination that the first SATA port is of the particular generation, determine whether the serial numbers match.

5 . The apparatus of claim 4 , wherein to determine whether a receiver equalization margin has been set for the device attached to the first SATA port, the BIOS, on determination that the serial numbers do not match, is to further mark the first SATA port as needing DTLE training; and on determination that the serial numbers do match, set the DTLE value of the first SATA port to the prior DTLE value, and up speed the first SATA port to the particular generation.

6 . The apparatus of claim 1 , wherein to perform a DTLE training to dynamically determine and set the receiver equalization margin for the device attached to the first SATA port, the BIOS is to up speed all SATA ports to an operating speed of a particular generation, and turn on a margin mode.

7 . The apparatus of claim 6 , wherein to perform a DTLE training to dynamically determine and set the receiver equalization margin for the device attached to the first SATA port, the BIOS is to further iteratively test the first SATA port for a number of predetermined DTLE value candidates, starting with a lowest one of the DTLE value candidates, and at each iteration, determine whether a current DTLE value candidate exceeds a maximum DTLE value, and on determination that the current DTLE value candidate does not exceed the maximum DTLE value, increment the current DTLE value candidate to a next higher one of the DTLE value candidates, wherein the number of predetermined DTLE value candidates iterated sweeps a subset but not an entire receiver equalization range.

8 . The apparatus of claim 7 , wherein during each iteration, prior to increment of the current DTLE value candidate to a next higher one of the DTLE value candidates, the BIOS is to further determine whether status of the first SATA port indicates error, and on determination that the status of the first SATA port does not indicate error, the BIOS is to continue with increment of the current DTLE value candidate to a next higher one of the DTLE value candidates.

9 . The apparatus of claim 8 , wherein on determination that the status of the first SATA port indicates error, the BIOS is to further determine whether the speed of the first SATA port has been down trained, and on determination that the speed of the first SATA port has been down trained, recover the speed of the first SATA port to a particular generation of SATA ports.

10 . The apparatus of claim 7 , wherein the BIOS, on determination that the current DTLE value candidate exceeds the maximum DTLE value, is to select a DTLE for the first SATA port among the DTLE candidate values iterated.

11 . A method for computing, comprising:
during boot up of a computing system, determining, by a basic input-output system (BIOS) of the computing system, during a power on self test (POST) phase of the boot up, whether a device is attached to a serial advance technology attachment (SATA) port; on determining that a device is attached to the SATA port, further determining, by the BIOS, whether a receiver equalization margin has been set for the device; and on determining that a receiver equalization margin has not been set for the device, performing a discrete time linear equalization training to dynamically determine and set the receiver equalization margin for the device.

12 . The method of claim 11 , wherein determining whether a receiver equalization margin has been set for the device attached to the first SATA port, comprises:
getting prior device information associated with the first SATA port, including a device serial number and the DTLE value previously associated with the first SATA port; identifying and obtaining serial number for the device currently attached to the first SATA port; determining whether the first SATA port is of a particular generation; and on determining that the first SATA port is of the particular generation, determining whether the serial numbers match.

13 . The method of claim 12 , wherein determining whether a receiver equalization margin has been set for the device attached to the first SATA port, comprise: the BIOS, on determining that the serial numbers do not match, marking the first SATA port as needing DTLE training; and on determining that the serial numbers do match, setting the DTLE value of the first SATA port to the prior DTLE value, and upping speed the first SATA port to the particular generation.

14 . The method of claim 11 , wherein performing a DTLE training to dynamically determine and set the receiver equalization margin for the device attached to the first SATA port, comprises: upping speed all SATA ports to an operating speed of a particular generation, and turning on a margin mode.

15 . The method of claim 14 , wherein performing a DTLE training to dynamically determine and set the receiver equalization margin for the device attached to the first SATA port, comprises iteratively testing the first SATA port for a number of predetermined DTLE value candidates, starting with a lowest one of the DTLE value candidates, and at each iteration, determining whether a current DTLE value candidate exceeds a maximum DTLE value, and on determining that the current DTLE value candidate does not exceed the maximum DTLE value, incrementing the current DTLE value candidate to a next higher one of the DTLE value candidates, wherein the number of predetermined DTLE value candidates iterated sweeps a subset but not an entire receiver equalization range.

16 . At least one computer-readable stora

Assignees

• Intel Corp

Inventors

• Sim Chee Keong
• Ng Kai Chong
• Hau Tze Ming

Classifications

• G06F9/4413

  Plug-and-play [PnP] · CPC title

• G06F11/2284 Primary

  by power-on test, e.g. power-on self test [POST] · CPC title

• G06F9/4401

  Bootstrapping (security arrangements therefor G06F21/57) · CPC title