Apparatus and methods for pll-based gyroscope gain control, quadrature cancellation and demodulation

Patent metadata

Field	Value
Publication number	US-2016161256-A1
Application number	US-201414217842-A
Country	US
Kind code	A1
Filing date	Mar 18, 2014
Priority date	Mar 15, 2013
Publication date	Jun 9, 2016
Grant date	—

Abstract

This application discusses, among other things, simplified interface circuits for a gyroscope. In an example, a interface can include an automatic gain control (AGC) circuit configured to couple to driver for a proof mass of a gyroscope sensor and to drive the proof-mass to oscillate at a predefined oscillation amplitude, and a phase-locked loop (PLL) configured to receive sensed oscillation information from the proof-mass and to provide at least a first phase signal synchronized with a sinusoidal waveform of the sensed oscillation information.

First claim

What is claimed is:

1 . A micro-electromechanical system (MEMS) sensor interface comprising:
an automatic gain control (AGC) circuit configured to couple to driver for a proof mass of a gyroscope and to drive the proof-mass to oscillate at a predefined oscillation amplitude; and a phase-locked loop (PLL) configured to receive sensed oscillation information from the proof-mass and to provide at least a first phase signal synchronized with a sinusoidal waveform of the sensed oscillation information.

2 . The interface of claim 1 , wherein the PLL includes:
a phase generator configured to receive a PLL clock signal and to provide the first phase signal synchronized in phase with the PLL clock signal; a voltage controlled oscillator configured to provide the PLL clock signal; a loop filter configured to receive a coarse PLL command signal and a phase error signal and to provide a PLL command signal to the VCO using the coarse PLL command signal and the phase error signal; a coarse phase frequency detector (PFD) configured to receive a square-wave representation of the oscillation information and to provide the coarse PLL command signal to the VCO; and a fine phase detector configured to receive an analog representation of the oscillation information, to receive the first phase signal and to provide the phase error information.

3 . The interface of claim 1 , wherein the fine PD includes:
at least two sample circuits, each circuit including a sample capacitor; a sample switch configured to receive the analog representation of the oscillation information, to couple the first sample capacitor to the analog representation of the oscillation information in a first state of the sample switch and to isolate the the first sample capacitor from the analog representation of the oscillation information in a second state of the sample switch; an output capacitor; and a dump switch coupled between the sample capacitor and the output capacitor, the dump switch configured to couple the sample capacitor with the output capacitor in a first state of the dump switch and to isolate the output capacitor from the sample capacitor in a second state of the dump switch.

4 . The interface of claim 3 , wherein the first state of the sample switch is responsive to the first phase signal, wherein the first phase signal is representative of a zero-crossing of the analog representation of the oscillation information.

5 . The interface of claim 4 , wherein a voltage of the output capacitor is indicative of an amplitude of the analog representation of the oscillation information at a transition of the sample switch.

6 . The interface of claim 5 , wherein the fine PD includes a phase error summer configured to couple to the output capacitor of each of the at least two sample circuits and to provide the phase error information.

7 . The interface of claim 1 , wherein the AGC circuit includes:
an up/down counter configured to provide a coarse gain signal to a proof mass drive when a fine gain signal remains at a high or low extreme for a predetermined number of oscillations of the proof-mass; an amplifier configured to receive rectified amplitude information of the proof mass, to receive an amplitude threshold, and to compare the rectified amplitude information to the amplitude threshold to provide the fine gain signal; and a rectifier including a plurality of capacitors for providing the rectified amplitude information.

8 . The interface of claim 7 , wherein the rectifier is configured to receive a second phase signal from the PLL, wherein the second phase signal is representative of a 90 degree offset from a zero-crossing of the analog representation of the oscillation information.

9 . A method for oscillating a proof-mass of a micro-electromechanical system (MEMS) sensor, the method comprising:
providing an oscillation drive signal at a proof mass driver from an automatic gain control circuit; receiving sensed oscillation information from the proof-mass at a phase-locked loop (PLL); providing at least a first phase signal synchronized with a sinusoidal waveform of the sensed oscillation information using the PLL. receiving the sensed oscillation information from the proof-mass at the AGC; and comparing the sensed oscillation information with a threshold amplitude to provide an amplitude error signal using the first phase signal.

10 . The method of claim 9 , wherein the PLL includes:
receiving a PLL clock signal at a phase generator of the PLL provide phase synchronizing the first phase signal with the PLL clock signal using a coarse phase frequency detector (PFD) and a find phase detector (PD); providing the PLL clock signal using a voltage controlled oscillator (VCO) of the PLL; receiving a coarse PLL command signal and a phase error signal at a loop filter providing a PLL command signal to the VCO using the coarse PLL command signal and the phase error signal and the loop filter; receiving a square-wave representation of the oscillation information at the coarse PFD; providing the coarse PLL command signal to the VCO using the coarse PFD; receiving an analog representation of the oscillation information and a second phase signal at the fine PD; and providing the phase error information using the fine PD.

11 . The method of claim 10 , wherein providing the phase error information includes summing adjacent samples of the analog representation of the oscillation information, wherein the adjacent samples are triggered using the second phase signal;
wherein the second phase signal is representative of zero-crossing events of the analog representation of the oscillation information; and wherein the adjacent samples represent amplitudes of the analog representation of the oscillation information at representative adjacent zero-crossing events.

12 . The method of claim 11 , wherein the summing the adjacent samples includes;
collecting a first sample near a first zero-crossing using a first sample capacitor and a first sample switch responsive to the second phase signal; and collecting a second sample near a second zero-crossing adjacent the first zero-crossing using a second sample capacitor and a second sample switch responsive to the second phase signal.

13 . The method of claim 12 , wherein the collecting the first sample includes
coupling the first sample capacitor to the analog representation of the oscillation information near the first zero-crossing for a first interval of time; isolating the first sample capacitor from the analog representation of the oscillation information after completion of the first interval; coupling the second sample capacitor to the analog representation of the oscillation information near the second zero-crossing for a second interval of time; isolating the second sample capacitor from the analog representation of the oscillation information after completion of the second interval; and

14 . The method of claim 13 , wherein the providing the adjacent samples includes simultaneously dumping a voltage of the first sampling capacitor and a voltage of the second sampling capacitor to respective first and second output capacitors using first and second dump switches.

15 . The method of claim 1 , wherein the providing the oscillation drive signal includes:
providing a coarse gain signal and a fine gain signal from the AGC to the proof mass driver;

16 . The method of claim 15 wherein providing the coarse gain signal includes adjusting the coarse gain signal using an up down counter when the fine gain signal of the AGC remain

Assignees

• Fairchild Semiconductor

Inventors

• Lee Shungneng
• Tao Hai
• Opris Ion
• Pavan Shanthi

Classifications

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/087

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• G01C19/5776 Primary

  Signal processing not specific to any of the devices covered by groups G01C19/5607 - G01C19/5719 · CPC title

• B81B7/008 Primary

  MEMS characterised by an electronic circuit specially adapted for controlling or driving the same (B81B7/0087 takes precedence; arrangements for starting, regulating, braking, or otherwise controlling an actuator H02N; control arrangements or circuits for visual indicators G09G3/00) · CPC title