Method of Fabricating Fin-Field Effect Transistors (FINFETS) Having Different Fin Widths

Patent metadata

Field	Value
Publication number	US-2016155804-A1
Application number	US-201615013647-A
Country	US
Kind code	A1
Filing date	Feb 2, 2016
Priority date	Mar 19, 2012
Publication date	Jun 2, 2016
Grant date	—

Abstract

Provided are methods of forming field effect transistors. The method includes preparing a substrate with a first region and a second region, forming fin portions on the first and second regions, each of the fin portions protruding from the substrate and having a first width, forming a first mask pattern to expose the fin portions on the first region and cover the fin portions on the second region, and changing widths of the fin portions provided on the first region.

First claim

1 - 11 . (canceled)

12 . A semiconductor device, comprising:
a substrate including a first region and a second region; a plurality of fins protruding from a top surface of the substrate, the plurality of fins including a first fin, a second fin and a third fin that are disposed in the first region, and including a fourth fin, a fifth fin and a sixth fin that are disposed in the second region, the second fin being disposed between the first fin and the third fin, the fifth fin being disposed between the fourth fin and the sixth fin; a first isolation disposed between the first fin and the second fin; a second isolation disposed between the second fin and the third fin; a third isolation disposed between the fourth fin and the fifth fin; a fourth isolation disposed between the fifth fin and the sixth fin, wherein a width of an upper portion of the second fin is different from a width of an upper portion the fourth fin.

13 . The semiconductor device of claim 12 , wherein the upper portion of the second fin is disposed higher than a top surface of the first isolation and higher than a top surface of the second isolation, and
the upper portion of the fourth fin is disposed higher than a top surface of the third isolation.

14 . The semiconductor device of claim 12 , wherein an N type transistor is formed in the first region,
a P type transistor is formed in the second region.

15 . The semiconductor device of claim 14 , wherein the width of the upper portion of the second fin is greater than the width of the upper portion the fourth fin.

16 . The semiconductor device of claim 14 , wherein the width of the upper portion of the second fin is less than the width of the upper portion the fourth fin.

17 . The semiconductor device of claim 12 , wherein a height of the second fin is different from a height of the fourth fin.

18 . The semiconductor device of claim 14 , wherein a height of the second fin is greater than a height of the fourth fin.

19 . The semiconductor device of claim 14 , wherein a height of the second fin is less than a height of the fourth fin.

20 . The semiconductor device of claim 12 , wherein the width of the upper portion of the second fin and the width of the upper portion of the fourth fin are different from each other at the same height level.

21 . The semiconductor device of claim 12 , further comprising a gate electrode formed on the first, second, third and fourth device isolations, and crossing the plurality of fins.

22 . A semiconductor device, comprising:
a substrate including a first region and a second region; a plurality of fins disposed on the substrate, and including a first fin, a second fin, a third fin, a fourth fin, a fifth fin and a sixth fin; a plurality of device isolations disposed on the substrate, each of the plurality of device isolations being disposed between two fins among the plurality of fins; and a gate electrode formed on the plurality of device isolations and crossing the plurality of fins, wherein the first fin, the second fin and the third fin are disposed on the first region, the fourth fin, the fifth fin and the sixth fin are disposed on the second region, the second fin is disposed between the first fin and the third fin, the fifth fin is disposed between the fourth fin and the sixth fin, lower portions of the plurality of fins are covered by the plurality of device isolations, and a width of an upper portion of the second fin and a width of an upper portion of the fourth fin are different from each other at the same height level.

23 . The semiconductor device of claim 22 , wherein the plurality of device isolations include a first device isolation contacting the second fin and a second device isolation contacting the fourth fin, and
a width of the second fin measured at the same level as a top surface of the first device isolation is different from a width of the fourth fin measured at the same level as a top surface of the second device isolation.

24 . The semiconductor device of claim 22 , wherein an N type transistor is formed in the first region, and
a P type transistor is formed in the second region.

25 . The semiconductor device of claim 22 , wherein a sidewall of the second fin has a bending point at which the sidewall of the second fin is concavely bent, and
a sidewall of the fourth fin has a bending point at which the sidewall of the fourth fin is concavely bent.

26 . The semiconductor device of claim 22 , wherein the gate electrode includes a first portion disposed between the first fin and the second fin and a second portion disposed between the fourth fin and the fifth fin, and
a width of the first portion of the gate electrode is different from a width of the second portion of the gate electrode.

27 . A semiconductor device, comprising:
a substrate including a first region and a second region; a plurality of fins protruding from a top surface of the substrate, and including a first fin, a second fin, a third fin, a fourth fin, a fifth fin and a sixth fin, a width of a lower portion of each of the plurality of fins being greater than a width of an upper portion of each of the plurality of fins; and a plurality of device isolations disposed on the substrate and including a first device isolation contacting the second fin and a second device isolation contacting the fourth fin, each of the plurality of device isolations being disposed between two fins among the plurality of fins, wherein an N type transistor is formed in the first region, a P type transistor is formed in the second region, the first fin, the second fin and the third fin are disposed on the first region, the fourth fin, the fifth fin and the sixth fin are disposed on the second region, the second fin is disposed between the first fin and the third fin, the fifth fin is disposed between the fourth fin and the sixth fin, and a width of the second fin measured at the same level as a top surface of the first device isolation is different from a width of the fourth fin measured at the same level as a top surface of the second device isolation.

28 . The semiconductor device of claim 27 , wherein a width of an upper portion of the second fin is different from a width of an upper portion the fourth fin.

29 . The semiconductor device of claim 27 , wherein a depth of the first device isolation is different from a depth of the second device isolation.

30 . The semiconductor device of claim 27 , wherein a width of the first device isolation is different from a width of the second device isolation.

31 . The semiconductor device of claim 27 , wherein a threshold voltage of the N type transistor is different from a threshold voltage of the P type transistor.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Oh Chang Woo
• Min Shincheol
• Lee Jongwook
• Lee Choongho

Classifications

• H10P50/695 Primary

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10P14/60

  of insulating materials · CPC title

• H10D30/0245

  by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins · CPC title

• H10D84/853

  comprising FinFETs · CPC title