Display panel

Patent metadata

Field	Value
Publication number	US-2016155752-A1
Application number	US-201514641453-A
Country	US
Kind code	A1
Filing date	Mar 9, 2015
Priority date	Nov 28, 2014
Publication date	Jun 2, 2016
Grant date	—

Abstract

A display panel is provided. The display panel has a display area and a peripheral area and includes a plurality of pixels, a plurality of data lines and a plurality of signal traces. The pixels are disposed on the display area and arranged in an array. The data lines extend from the display area to the peripheral area and are respectively electrically connected to a plurality of columns of pixel. The signal traces extend from the display area to the peripheral area and are parallel to the data lines. In addition, the data lines and the signal traces are respectively disposed between two columns of pixels, and the signal traces include a plurality of gate signal traces.

First claim

What is claimed is:

1 . A display panel, having a display area and a peripheral area, the display panel comprising:
a plurality of pixels, disposed in the display area and arranged in an array; a plurality of data lines, extending from the display area to the peripheral area to be electrically connected to a source driver, wherein the data lines are respectively electrically connected to a plurality of columns of pixels; a plurality of gate lines, disposed in the display area and perpendicular to the data lines; and a plurality of signal traces, extending from the display area to the peripheral area and parallel to the data lines, wherein the data lines and the signal traces are respectively disposed between two columns of pixels, and the signal traces comprise a plurality of gate signal traces respectively electrically connected to the corresponding gate lines.

2 . The display panel as claimed in claim 1 , wherein the gate signal traces electrically connected to a plurality of odd gate lines of the gate lines are sequentially arranged from a first side of the display area to the center of the display panel, the gate signal traces electrically connected to a plurality of even gate lines of the gate lines are sequentially arranged from a second side of the display area to the center of the display panel, and the first side and the second side are opposite sides of the display panel.

3 . The display panel as claimed in claim 1 , wherein the signal traces further comprise a plurality of floated metal wires.

4 . The display panel as claimed in claim 1 , wherein the signal traces further comprise a plurality of common voltage lines.

5 . The display panel as claimed in claim 1 , wherein the signal traces further comprise a plurality of floated metal wires and a plurality of common voltage lines.

6 . The display panel as claimed in claim 1 , wherein a plurality of active devices of the pixels are cascaded along a first direction perpendicular to the data lines to be electrically connected to the corresponding data lines.

7 . The display panel as claimed in claim 6 , wherein control ends of the cascaded active devices are respectively electrically connected to different gate lines.

8 . The display panel as claimed in claim 7 , wherein the control ends of the cascaded active devices are electrically connected to the adjacent gate lines.

9 . The display panel as claimed in claim 6 , wherein the cascaded pixels correspond to different colors.

Assignees

• Au Optronics Corp

Inventors

• Huang Te-Chun
• Huang Kuo-Yu
• Huang Yu-Han
• Chen Maw-Song
• Huang Wei-Ming

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H01L27/124 Primary

  Electricity · mapped topic

• G02F1/1345 Primary

  Conductors connecting electrodes to cell terminals · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title