Laminated ceramic capacitor and method for manufacturing laminated ceramic capacitor

US2016155571A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016155571-A1
Application numberUS-201615004040-A
CountryUS
Kind codeA1
Filing dateJan 22, 2016
Priority dateAug 2, 2013
Publication dateJun 2, 2016
Grant date

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  1. Title

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A laminated ceramic capacitor having internal electrodes configured such that Sn is dissolved in Ni, and, in a region of each of the internal electrodes at a depth of 2 nm from a surface thereof facing a ceramic dielectric layer, a CV value representing variation of a Sn/(Ni+Sn) ratio (ratio of number of atoms) is less than or equal to 32%. As a conductive paste for forming the internal electrodes, a conductive paste containing a Ni powder and a tin oxide powder which is represented by SnO or SnO 2 and has a specific surface area of more than or equal to 10 m 2 /g as determined by a BET method is used, or a conductive paste containing a Ni—Sn alloy powder is used, or a conductive paste containing a Ni—Sn alloy powder and a tin oxide powder which is represented by SnO or SnO 2 and has a specific surface area of more than or equal to 10 m 2 /g is used.

First claim

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1 . A laminated ceramic capacitor, comprising: a ceramic laminated body having a plurality of ceramic dielectric layers and a plurality of internal electrodes arranged to face each other with a ceramic dielectric layer of the plurality of ceramic dielectric layers being interposed therebetween; and at least two external electrodes arranged on an external surface of the ceramic laminated body, a first of the at least two external electrodes being in conduction with a first set of the plurality of internal electrodes, and a second of the at least two external electrodes being in conduction with a second set of the plurality of internal electrodes, wherein Sn is dissolved in Ni in the internal electrodes, and in a region of each of the plurality of internal electrodes at a depth of 2 nm from a surface thereof facing the ceramic dielectric layer interposed therebetween, a ratio of a content of a number of atoms of Sn to a total content of Sn and Ni is less than or equal to 32%. 2 . The laminated ceramic capacitor according to claim 1 , wherein the plurality of ceramic dielectric layers have a barium titanate-based perovskite compound as a main component thereof. 3 . A method for manufacturing a laminated ceramic capacitor, the method comprising: forming an unfired ceramic laminated body having a plurality of unfired ceramic dielectric layers and a plurality of unfired internal electrode patterns arranged along a plurality of interfaces between the unfired ceramic dielectric layers, the plurality of unfired internal electrode patterns being formed by applying a conductive paste containing a Ni powder and a tin oxide powder which is represented by SnO or SnO 2 and has a specific surface area of more than or equal to 10 m 2 /g as determined by a BET method; and firing the unfired ceramic laminated body to obtain a ceramic laminated body having a plurality of ceramic dielectric layers and a plurality of internal electrodes arranged along a plurality of interfaces between the ceramic dielectric layers. 4 . The method for manufacturing the laminated ceramic capacitor according to claim 3 , wherein the plurality of unfired ceramic dielectric layers have a barium titanate-based perovskite compound as a main component thereof. 5 . The method for manufacturing the laminated ceramic capacitor according to claim 3 , further comprising forming at least two external electrodes on an external surface of the ceramic laminated body, a first of the at least two external electrodes being in conduction with a first set of the plurality of internal electrodes, and a second of the at least two external electrodes being in conduction with a second set of the plurality of internal electrodes. 6 . The method for manufacturing the laminated ceramic capacitor according to claim 3 , wherein, after firing, the Sn is dissolved in Ni in the internal electrodes, and in a region of each of the plurality of internal electrodes at a depth of 2 nm from a surface thereof facing a ceramic dielectric layer interposed therebetween, a ratio of a content of a number of atoms of Sn to a total content of Sn and Ni is less than or equal to 32%. 7 . A method for manufacturing a laminated ceramic capacitor, the method comprising: forming an unfired ceramic laminated body having a plurality of unfired ceramic dielectric layers and a plurality of unfired internal electrode patterns arranged along a plurality of interfaces between the unfired ceramic dielectric layers, the plurality of unfired internal electrode patterns being formed by applying a conductive paste containing a Ni—Sn alloy powder; and firing the unfired ceramic laminated body to obtain a ceramic laminated body having a plurality of ceramic dielectric layers and a plurality of internal electrodes arranged along a plurality of interfaces between the ceramic dielectric layers. 8 . The method for manufacturing the laminated ceramic capacitor according to claim 7 , wherein the plurality of ceramic dielectric layers have a barium titanate-based perovskite compound as a main component thereof. 9 . The method for manufacturing the laminated ceramic capacitor according to claim 7 , further comprising forming at least two external electrodes on an external surface of the ceramic laminated body, a first of the at least two external electrodes being in conduction with a first set of the plurality of internal electrodes, and a second of the at least two external electrodes being in conduction with a second set of the plurality of internal electrodes. 10 . The method for manufacturing the laminated ceramic capacitor according to claim 7 , wherein, after firing, the Sn is dissolved in Ni in the internal electrodes, and in a region of each of the plurality of internal electrodes at a depth of 2 nm from a surface thereof facing a ceramic dielectric layer interposed therebetween, a ratio of a content of a number of atoms of Sn to a total content of Sn and Ni is less than or equal to 32%. 11 . The method for manufacturing the laminated ceramic capacitor according to claim 7 , wherein the conductive paste containing the Ni—Sn alloy powder further contains a tin oxide powder which is represented by SnO or SnO 2 and has a specific surface area of more than or equal to 10 m 2 /g as determined by a BET method. 12 . The method for manufacturing the laminated ceramic capacitor according to claim 11 , wherein the plurality of ceramic dielectric layers have a barium titanate-based perovskite compound as a main component thereof. 13 . The method for manufacturing the laminated ceramic capacitor according to claim 11 , further comprising forming at least two external electrodes on an external surface of the ceramic laminated body, a first of the at least two external electrodes being in conduction with a first set of the plurality of internal electrodes, and a second of the at least two external electrodes being in conduction with a second set of the plurality of internal electrodes. 14 . The method for manufacturing the laminated ceramic capacitor according to claim 11 , wherein, after firing, the Sn is dissolved in Ni in the internal electrodes, and in a region of each of the plurality of internal electrodes at a depth of 2 nm from a surface thereof facing a ceramic dielectric layer interposed therebetween, a ratio of a content of a number of atoms of Sn to a total content of Sn and Ni is less than or equal to 32%.

Assignees

Inventors

Classifications

  • Stacked capacitors (H01G4/33 takes precedence) · CPC title

  • electrically connecting two or more layers of a stacked or rolled capacitor · CPC title

  • Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title

  • H01G4/1227Primary

    based on alkaline earth titanates · CPC title

  • Single unit multiple capacitors, e.g. dual capacitor in one coil · CPC title

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What does patent US2016155571A1 cover?
A laminated ceramic capacitor having internal electrodes configured such that Sn is dissolved in Ni, and, in a region of each of the internal electrodes at a depth of 2 nm from a surface thereof facing a ceramic dielectric layer, a CV value representing variation of a Sn/(Ni+Sn) ratio (ratio of number of atoms) is less than or equal to 32%. As a conductive paste for forming the internal electro…
Who is the assignee on this patent?
Murata Manufacturing Co
What technology area does this patent fall under?
Primary CPC classification H01G4/1227. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jun 02 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).