System error handling in a data processing apparatus

Patent metadata

Field	Value
Publication number	US-2016154654-A1
Application number	US-201514952807-A
Country	US
Kind code	A1
Filing date	Nov 25, 2015
Priority date	Nov 28, 2014
Publication date	Jun 2, 2016
Grant date	—

Abstract

Apparatus for data processing and a method of data processing are provided. Data processing operations are performed in response to data processing instructions. An error exception condition is set if a data processing operation has not been successful. It is determined if an error memory barrier condition exists and an error memory barrier procedure is performed in dependence on whether the error memory barrier condition exists. The error memory barrier procedure comprises, if the error exception condition is set and if an error mask condition is set: setting a deferred error exception condition and clearing the error exception condition.

First claim

1 . Apparatus for data processing comprising:
processing circuitry to perform data processing operations in response to data processing instructions, to determine if an error memory barrier condition exists and to perform an error memory barrier procedure in dependence on whether the error memory barrier condition exists, wherein the processing circuitry is capable of setting an error exception condition upon detection that a data processing operation has not been successful, and wherein the error memory barrier procedure comprises, if the error exception condition is set and if an error mask condition is set:
setting a deterred error exception condition; and
clearing the error exception condition.

2 . The apparatus as claimed in claim 1 , wherein the processing circuitry, if error exception condition is set and the error mask condition is not set, is capable of performing an exception handling procedure.

3 . The apparatus as claimed in claim 1 , wherein the data processing operations comprise memory accesses, and
wherein the processing circuitry is capable of receiving an error response for a memory access, and wherein the processing circuitry is capable of setting the error exception condition if the error response indicates that the memory access has not been successful.

4 . The apparatus as claimed in claim 1 , wherein the processing circuitry is capable of determining that the error memory barrier condition exists in response to an error memory barrier instruction in the data processing instructions.

5 . The apparatus as claimed in claim 2 , wherein the processing circuitry is capable of, as part of the exception handling procedure and if the deferred error exception condition is set, initiating a remedial response with respect to at least one data processing instruction, wherein the at least one data processing instruction comprises a data processing instruction executed prior to determining that the error memory barrier condition existed.

6 . The apparatus as claimed in claim 2 , further comprising error memory barrier mode value storage, wherein when the processing circuitry initiates performance of the exception handling procedure the processing circuitry is capable of determining that the error memory barrier condition exists in dependence on an error memory barrier mode value stored in the error memory barrier mode value storage.

7 . The apparatus as claimed in claim 3 , wherein the processing circuitry is capable of, when performing the error memory barrier procedure and if the error memory barrier condition exists, waiting for the error response for each memory access which has not yet completed before executing further data processing instructions.

8 . The apparatus as claimed in claim 1 , further comprising error mask value storage, wherein the processing circuitry is capable of determining if the error mask condition is set in dependence on an error mask value stored in the error mask value storage.

9 . The apparatus as claimed in claim 2 , wherein the processing circuitry is capable of setting the error mask value when beginning the exception handling procedure.

10 . The apparatus as claimed in claim 2 , wherein the processing circuitry is capable of clearing the error mask value as part of the exception handling procedure if the deferred error exception condition is not set.

11 . The apparatus as claimed in claim 1 , wherein the processing circuitry is capable of setting the error mask value and clearing the error mask value after a predetermined set of data processing instructions have been completed if the deferred error exception condition is not set.

12 . The apparatus as claimed in claim 2 , wherein the processing circuitry is capable of performing the exception handling procedure at a current exception level selected from plural exception levels, wherein the plural exception levels correspond to plural software execution privilege levels.

13 . The apparatus as claimed in claim 12 , wherein the processing circuitry is capable of setting the error mask condition when initiating the exception handling procedure if the exception handling procedure is to be performed by the processing circuitry at an exception level which is the same as or higher than the exception level at which a further exception handling procedure in response to a further error exception condition is to be performed.

14 . The apparatus as claimed in claim 12 , wherein the processing circuitry is capable of not setting the error mask condition when initiating the exception handling procedure if the exception handling procedure is to be performed by the processing circuitry at an exception level which is lower than the exception level at which a further exception handling procedure in response to a further error exception condition is to be performed.

15 . The apparatus as claimed in claim 1 , capable of providing a virtualized operating environment in which at least one virtual machine operates, wherein the virtual machine is capable of performing the data processing operations in response to the data processing instructions by interaction with the processing circuitry.

16 . The apparatus as claimed in claim 15 , wherein the processing circuitry, if the error exception condition is set and the error mask condition is not set, is capable of performing an exception handling procedure, wherein the apparatus is capable of setting a virtual error exception condition and wherein the processing circuitry, if the virtual error exception condition is set and a virtual error mask condition is not set, is capable of performing the exception handling procedure.

17 . The apparatus as claimed in claim 15 , wherein the error memory barrier procedure further comprises, if the virtual error exception condition is set and if the virtual error mask condition is set:
setting a virtual deferred error exception condition; and clearing the virtual error exception condition.

18 . The apparatus as claimed in claim 17 , wherein the apparatus is capable of providing a value of the virtual deferred error exception condition in place of a value of the deferred error exception condition, when the processing circuitry seeks to determine if the deferred error exception condition is set.

19 . A method of data processing comprising the steps of:
performing data processing operations in response to data processing instructions; setting an error exception condition upon detection that a data processing operation has not been successful; determining if an error memory barrier condition exists; and performing an error memory harrier procedure in dependence on whether the error memory barrier condition exists, wherein the error memory barrier procedure comprises, if the error exception condition is set and if an error mask condition is set:
setting a deferred error exception condition; and
clearing the error exception condition.

20 . Apparatus for data processing comprising:
means for performing data processing operations in response to data processing instructions; means for setting an error exception condition upon detection that a data processing operation has not been successful; means for determining if an error memory barrier condition exists; and means for performing an error memory barrier procedure in dependence on whether the error memory barrier condition exists, wherein the error memory barrier procedure comprises, if the error exception condition is set and if an error mask condition is set:
setting a deferred err

Assignees

• Advanced Risc Mach Ltd

Inventors

• Williams Michael John
• Grisenthwaite Richard Roy
• Craske Simon John

Classifications

• G06F11/0793 Primary

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F11/0721 Primary

  within a central processing unit [CPU] · CPC title

• G06F9/3861 Primary

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F9/522

  Barrier synchronisation · CPC title

• G06F9/3865 Primary

  using deferred exception handling, e.g. exception flags · CPC title