High performance fluxgate device

Patent metadata

Field	Value
Publication number	US-2016154069-A1
Application number	US-201414557611-A
Country	US
Kind code	A1
Filing date	Dec 2, 2014
Priority date	Dec 2, 2014
Publication date	Jun 2, 2016
Grant date	—

Abstract

An integrated circuit includes a fluxgate magnetometer. The magnetic core of the fluxgate magnetometer is encapsulated with a layer of encapsulant of a nonmagnetic metal or a nonmagnetic alloy. The layer of encapsulate provides stress relaxation between the magnetic core material and the surrounding dielectric. A method for forming an integrated circuit has the magnetic core of a fluxgate magnetometer encapsulated with a layer of a nonmagnetic metal or nonmagnetic alloy to eliminate delamination and to substantially reduce cracking of the dielectric that surrounds the magnetic core.

First claim

What is claimed is:

1 . An integrated circuit, comprising:
a fluxgate with a magnetic core wherein the magnetic core is encapsulated on all sides by a layer of encapsulant wherein the encapsulant is comprised of a first layer of a nonmagnetic metal or a nonmagnetic alloy under the magnetic core and a second layer of the nonmagnetic metal or nonmagnetic alloy over the top and sides of the magnetic core.

2 . The integrated circuit of claim 1 , wherein the nonmagnetic metal is selected from the group consisting of Ti, Ta, Ru, and Pt and wherein the nonmagnetic alloy is selected from the group consisting of TiN, TaN, and AlN.

3 . The integrated circuit of claim 1 , wherein the magnetic core comprises a magnetic core material that is selected from the group consisting of permalloy, NiFeMo, CoNbZr, and CoTaZr.

4 . The integrated circuit of claim 3 , wherein the magnetic core is a multilayered stack of alternating layers of magnetic core material and a dielectric selected from the group consisting of aluminum oxide, silicon dioxide, and aluminum nitride.

5 . The integrated circuit of claim 4 , wherein the multilayered stack is comprised of 3 to 10 layers of permalloy with a thickness in the range of 225 nm to 425 nm and 3 to 10 layers of AlN with a thickness in the range of 6 to 12 nm.

6 . The integrated circuit of claim 5 , wherein aluminum nitride is the top layer of the multilayered stack.

7 . The integrated circuit of claim 1 , wherein the first layer of the encapsulant is disposed under the magnetic core extending past the magnetic core by at least 1.5 microns on all sides and the second layer of the encapsulant is disposed over the top and sides of the magnetic core and extending past the magnetic core by at least 1.5 microns on all sides.

8 . The integrated circuit of claim 7 , wherein the first layer has a thickness in the range of 30 nm to 50 nm and wherein the second layer has a thickness in the range of 90 nm to 300 nm.

9 . A method of forming an integrated circuit, comprising the steps:
forming a etch stop layer on the integrated circuit wafer; forming a first encapsulation layer of a first nonmagnetic metal or nonmagnetic alloy on the first etch stop layer; forming a layer of magnetic core material on the first encapsulation layer; forming a magnetic core pattern on the magnetic core material; removing the magnetic core material where exposed by the magnetic core pattern to form a magnetic core; removing the magnetic core pattern; forming a second encapsulation layer of nonmagnetic metal or nonmagnetic alloy on the first encapsulation layer and on the top and sides of the magnetic core; forming an encapsulation etch pattern on the second encapsulation layer where the encapsulation etch pattern covers the magnetic core and extends least 1.5 um past the magnetic core on all sides and exposes the second encapsulation layer outside the encapsulation etch pattern; removing the second encapsulation layer where exposed outside the encapsulation etch pattern with an etch; and removing the first encapsulation layer with the etch and where the etch stops on the etch stop layer.

10 . The method of claim 9 , wherein the first encapsulation layer and the second encapsulation layer are selected from the group consisting of Ti, Ta, Ru, Pt, TiN, TaN, and AlN.

11 . The method of claim 9 , wherein said magnetic core material is selected from the group consisting of permalloy, NiFeMo, CoNbZr, and CoTaZr.

12 . The method of claim 9 , wherein the magnetic core comprises alternating layers of the magnetic core material and a dielectric wherein the magnetic core material is selected from the group consisting of permalloy, NiFeMo, CoNbZr, and CoTaZr and wherein the dielectric material is selected from the group consisting of aluminum nitride, aluminum oxide, and silicon dioxide.

13 . The method of claim 12 , wherein the magnetic core comprises 3 to 10 layers of permalloy with a thickness of between about 225 nm and 425 nm and layers of AlN with a thickness between 5 nm and 15 nm.

14 . The method of claim 13 , wherein the top layer of the laminate is the dielectric material.

15 . The method of claim 9 , wherein the first encapsulation layer is formed with a thickness in the range of 30 nm to 50 nm and the second encapsulation layer is formed with a thickness in the range of 90 nm to 300 nm.

16 . The method of claim 9 , wherein the steps of removing the first encapsulation layer and the second encapsulation layer comprise plasma etching with a fluorine containing gas.

17 . An integrated circuit, comprising:
a first titanium layer; a magnetic core disposed on the first titanium layer wherein the first titanium layer extends at least 1.5 microns beyond the magnetic core on all sides and wherein the magnetic core is comprised of 3 to 10 layers of a laminate of NiFe and AlN; and a second titanium layer disposed on a top and sides of the magnetic core and extending at least 1.5 microns beyond the magnetic core on all sides.

18 . The integrated circuit of claim 17 , wherein the first titanium layer has a thickness between 30 and 50 nm and wherein the second titanium layer has a thickness between 90 and 300 nm.

19 . The integrated circuit of claim 17 where the first titanium layer and the second titanium layer extend 2 microns beyond the magnetic core on all sides.

20 . A method of forming an integrated circuit, comprising the steps:
forming a etch stop layer on the integrated circuit wafer wherein the etch stop layer is SiN with a thickness between about 70 nm and 130 nm; forming a first titanium layer on the first etch stop layer wherein the first titanium layer is between about 30 nm and 50 nm; forming a stack of magnetic core material on the first titanium layer wherein the stack of magnetic core material is comprised of 3 to 10 layers of a NiFe permalloy and AlN laminate wherein the NiFe permalloy has a thickness between 225 nm and 425 nm and the AlN has a thickness between 6 nm and 12 nm; forming a magnetic core pattern on the stack of magnetic core material; removing the stack of magnetic core material where exposed by the magnetic core pattern with a wet etch containing phosphoric acid, acetic acid, and nitric acid to form a magnetic core; removing the magnetic core pattern; forming a second titanium layer on the first titanium layer and on the top and sides of the magnetic core wherein the second titanium layer has a thickness of between 50 nm and 90 nm; forming a titanium etch pattern on the second titanium layer wherein the titanium etch pattern covers the magnetic core and extends at least 1.5 um past the magnetic core and exposes the second titanium layer outside the titanium etch pattern; removing the second titanium layer where it is exposed using a plasma etch with a fluorine containing gas; and removing the first titanium layer where exposed using the plasma etch wherein the titanium etch stops on the etch stop layer.

Assignees

• Texas Instruments Inc

Inventors

• Eissa Mona M
• Lee Dok Won

Classifications

• G01R33/0052

  Manufacturing aspects; Manufacturing of single devices, i.e. of semiconductor magnetic sensor chips (devices based on galvano-magnetic effect or the like H10N50/85) · CPC title

• G01R33/04 Primary

  using the flux-gate principle · CPC title

• H10D84/01

  Manufacture or treatment · CPC title

• H01L43/12

  Electricity · mapped topic

• H10B61/00

  Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title