Methods and apparatus for link training, initialization and management via a high speed bus interface

Patent metadata

Field	Value
Publication number	US-2016149654-A1
Application number	US-201414550698-A
Country	US
Kind code	A1
Filing date	Nov 21, 2014
Priority date	Nov 21, 2014
Publication date	May 26, 2016
Grant date	—

Abstract

Apparatus and methods for training, initializing, and managing a unidirectional, sink-driven A/V interface of a consumer electronics device. Since camera sensors do not have significant processing capability, the disclosed embodiments couple the camera sensors to a simplified source node as a camera assembly. In the described embodiments, an intelligent receiver (e.g., a master “sink” node) trains, initializes, and manages one or more relatively low complexity camera sensor modules. Various other refinements and simplifications include: (i) where link training is managed by the receiver of the link, not by the transmitter, and (ii) where training multiple links in the network is managed by a single receiver.

First claim

1 . A method for link initialization of a unidirectional interface of an electronic device, comprising:
discovering one or more nodes of a network; configuring a first node for link initialization by identifying a test pattern to transmit; configuring a second node for link initialization by identifying the test pattern to receive; causing the first and second nodes to perform a test characterized by the test pattern; and querying the second node for a status of the test.

2 . The method of claim 1 , where the test pattern comprises clock-like content, and the test comprises a clock recovery test.

3 . The method of claim 1 , where the test pattern comprises data-like content, and the test comprises a symbol lock test.

4 . The method of claim 1 , where the unidirectional interface comprises a multi-lane interface, the test pattern comprises time varying content, and the test comprises an interlane alignment test.

5 . The method of claim 1 , where the first node comprises a source component and the second node comprises a sink component.

6 . The method of claim 5 , further comprising generating video content from the source component.

7 . The method of claim 5 , further comprising aggregating multiple data streams using the sink component.

8 . The method of claim 1 , where the one or more nodes of the network comprise slave nodes.

9 . The method of claim 8 , further comprising enabling the network when each one of the one or more nodes have successfully completed link initialization.

10 . An apparatus, comprising:
a master sink node; one or more source nodes; and a non-transitory computer readable medium comprising one or more instructions which when executed by the master sink node are configured to cause the master sink node to:
discover the one or more source nodes;
configure at least one source node to transmit a test pattern; and
verify the transmitted test pattern.

11 . The apparatus of claim 10 , where the transmitted test pattern is verified by at least one other sink node.

12 . The apparatus of claim 11 , further comprising one or more instructions which when executed by the master sink node are configured to cause the master sink node to transmit another test pattern to the at least one other sink node.

13 . The apparatus of claim 10 , where the transmitted test pattern is verified by the master sink node.

14 . The apparatus of claim 10 , where the test pattern comprises clock-like content.

15 . The apparatus of claim 14 , where when the transmitted test pattern is unacceptable, the master sink node configures the at least one source node to change a voltage swing or pre-emphasis settings.

16 . The apparatus of claim 10 , where the test pattern comprises data-like content.

17 . The apparatus of claim 16 , where the verification of the transmitted test pattern comprises a Bit Error Rate (BER) measurement.

18 . A master sink node, comprising:
a processor; and a non-transitory computer readable medium comprising one or more instructions which when executed by the processor are configured to cause the processor to:
configure at least one source node to transmit a test pattern;
configure at least one other sink node to receive the test pattern; and
query the at least one other sink node for successful reception of the test pattern.

19 . The master sink node of claim 18 , where the at least one source node has less processing capability than the master sink node.

20 . The master sink node of claim 19 , where the master sink node is a master of a control bus shared with the at least one source node and the at least one other sink node.

Assignees

• Apple Inc

Inventors

• Whitby-Strevens Colin
• Tripathy Brijesh

Classifications

• H04W24/10 Primary

  Scheduling measurement reports {; Arrangements for measurement reports} · CPC title

• H04B17/21 Primary

  for calibration; for correcting measurements · CPC title

• Y02D30/70

  in wireless communication networks · CPC title

• G09G2370/10

  Use of a protocol of communication by packets in interfaces along the display data pipeline · CPC title

• H04B17/0085

  using test signal generators · CPC title