Turbo decoder with a low-power input format and associated method

Patent metadata

Field	Value
Publication number	US-2016149596-A1
Application number	US-201414555309-A
Country	US
Kind code	A1
Filing date	Nov 26, 2014
Priority date	Nov 26, 2014
Publication date	May 26, 2016
Grant date	—

Abstract

A turbo decoder stores received data in words in systematic memory and parity memory in a way that is known that it will be used for later iterations by turbo decoder engines arranged to operate in parallel. A loader receives and separates LLRs into systematic and parity data and stores them into a portion of a word per cycle until a word is full in a corresponding one of the systematic memory and parity memory. The turbo decoder engines read the LLRs from one word of the systematic memory and one word of the parity memory in a single cycle. The data can be rearranged within the words in an order format for the turbo decoder engines to later read them by providing sub-words corresponding to respective ones of the plurality of turbo decoder engines.

First claim

1 . A turbo decoder, comprising
a systematic memory configured to store systematic data in words; a parity memory configured to store parity data in words; a plurality of turbo decoder engines operatively coupled to the systematic memory and the parity memory and arranged to operate in parallel on the systematic data read from words of the systematic memory and the parity data read from words of the parity memory; and a loader operatively coupled to the systematic memory and the parity memory and configured to receive logarithms of likelihood ratios (LLRs) from a receiver, separate the LLRs into systematic data and parity data, and store the LLRs so separated into a portion of one of the words per cycle to fill the words over the cycles with the portions in a corresponding one of the systematic memory and the parity memory; and wherein the plurality of turbo decoder engines read the LLRs from one word of the systematic memory and one word of the parity memory in a single cycle.

2 . A turbo decoder according to claim 1 , wherein the loader is configured to rearrange within the words in an order format for the turbo decoder engines to later read the words by providing the LLRs required for each of the turbo decoder engines.

3 . A turbo decoder according to claim 1 , further comprising a splitter operatively coupled to the systematic memory and the parity memory and configured to read therefrom and split so read systematic data and parity data into sub-words corresponding to respective ones of the plurality of turbo decoder engines.

4 . A turbo decoder according to claim 3 ,
wherein the splitter is configured to perform more read operations from the systematic memory than the loader performs write operations; and wherein the splitter is configured to perform more read operations from the parity memory than the loader performs write operations.

5 . A turbo decoder according to claim 4 , wherein the loader is configured to rearrange within the words in an order format for the turbo decoder engines to later read the words by providing the LLRs required for each of the turbo decoder engines.

6 . A turbo decoder according to claim 3 ,
wherein the loader is configured to perform more transformations before a write to the systematic memory than the splitter performs transformations after a read from the systematic memory because of how the loader rearranged data for storage in the systematic memory; and wherein the loader is configured to perform more transformations before a write to the parity memory than the splitter performs transformations after a read from the parity memory because of how the loader rearranged data for storage in the parity memory.

7 . A turbo decoder according to claim 6 , wherein the loader is configured to rearrange within the words in an order format for the turbo decoder engines to later read the words by providing the LLRs required for each of the turbo decoder engines.

8 . A turbo decoder according to claim 1 , wherein the loader is configured to rearrange the LLRs before writing them to the systematic memory and the parity memory in a way optimized for efficient read operations for processing by the turbo decoder engines.

9 . A turbo decoder according to claim 1 , wherein the loader is configured to store the LLRs into a corresponding one of the systematic memory and the parity memory rearranged within rows and at row addresses in a form and order for the turbo decoder engines to later read the LLRs optimized for maximum a posterior (MAP) processes.

10 . A turbo decoder according to claim 9 ,
wherein the turbo decoder is configured to calculate extrinsics during even and odd maximum a posterior (MAP) processes that occur at different times; and wherein during the even and odd maximum a posterior (MAP) processes, one of the systematic memory and the parity memory is configured to be idle.

11 . A method of decoding comprising the steps of:
(a) storing systematic data in words in a systematic memory; (b) storing parity data in words in a parity memory; (c) decoding in parallel the systematic data read from words of the systematic memory and the parity data read from words of the parity memory; (d) receiving logarithms of likelihood ratios (LLRs); and (e) separating the LLRs received in said receiving step (d) into systematic data and parity data, and storing the LLRs so separated into a portion of one of the words per cycle to fill the words over the cycles with the portions in a corresponding one of the systematic memory and the parity memory; and (f) wherein the decoding of said step (c) reads the LLRs from one word of the systematic memory and one word of the parity memory in a single cycle.

12 . A method of decoding according to claim 11 , wherein said step (e) of separating comprises the substep of (d)(1) rearranging the LLRs within the words in an order format for said step (c) of parallel decoding to later read the words by providing the LLRs required by each parallel decoding of said step (c).

13 . A method of decoding according to claim 12 , wherein said step (e) of separating performs more read operations from the systematic memory than said step (e) performs write operations and performs more read operations from the parity memory than said step (e) performs write operations.

14 . A method of decoding according to claim 12 , wherein said step (e) of separating performs more transformations before a write to the systematic memory than said step (e) performs transformations after a read from the systematic memory and performs more transformations before a write to the parity memory than said step (e) performs transformations after a read from the parity memory, because of how said step (e) rearranged data for storage in the systematic memory and in the parity memory.

15 . A method of decoding according to claim 11 , further comprising the step of (g) splitting systematic data and parity data read from the systematic memory and the parity memory into sub-words corresponding to respective parallel decoding steps of said step (c).

16 . A method of decoding according to claim 11 , wherein said step (e) of separating rearranges the LLRs before writing them to the systematic memory and the parity memory in a way optimized for efficient read operations for processing by the decoding of said step (c).

17 . A method of decoding according to claim 11 , wherein said step (e) of separating stores the LLRs into a corresponding one of the systematic memory and the parity memory rearranged within rows and at row addresses in a form and order for the decoding of said step (c) to later read the LLRs optimized for maximum a posterior (MAP) processes.

18 . A method of decoding according to claim 17 , wherein said step (c) of decoding further comprises the substep of (c)(1) calculating extrinsics during even and odd maximum a posterior (MAP) processes that occur at different times.

19 . A method of decoding according to claim 18 , wherein said method of decoding further comprises the step of (g) idling one of the systematic memory and the parity memory during the even and odd maximum a posterior (MAP) processes to save power.

Assignees

• Freescale Semiconductor Inc

Inventors

• Bahary Robert
• Jackowski Eric J

Classifications

• H03M13/6563

  Implementations using multi-port memories · CPC title

• H03M13/6566

  Implementations concerning memory access contentions · CPC title

• H03M13/6505

  Memory efficient implementations · CPC title

• H03M13/6561

  Parallelized implementations · CPC title

• H03M13/2978

  Particular arrangement of the component decoders · CPC title