Turbo decoders with stored column indexes for interleaver address generation and out-of-bounds detection and associated methods

Patent metadata

Field	Value
Publication number	US-2016149591-A1
Application number	US-201414555346-A
Country	US
Kind code	A1
Filing date	Nov 26, 2014
Priority date	Nov 26, 2014
Publication date	May 26, 2016
Grant date	—

Abstract

A turbo decoder decodes encoded data using a regenerated interleaver sequence. An addressable column index memory stores column indexes of the encoded data during an input phase of a turbo decode operation. An address generator generates the regenerated interleaver sequence based on the column indexes and computed data. In embodiments the address generator can read column indexes from the addressable column index memory, compute the computed data by permuting row indexes in a same row permuting order as an encoder that encoded the encoded data, combine the column indexes so read and the row indexes so permuted, use a row counter, and identify out of bounds addresses using the regenerated interleaver sequence.

First claim

1 . A turbo decoder for decoding encoded data, comprising:
a plurality of turbo decoder engines configured to turbo decode the encoded data using a regenerated interleaver sequence; a loader configured to generate column indexes based on a predetermined interleaver sequence; an addressable column index memory operatively coupled to the loader and the turbo decoder engines and configured to store the column indexes stored during an input phase of turbo decode operations of the turbo decoder engines; and a plurality of address generators each operatively coupled to the addressable column index memory and a corresponding turbo decoder engine and configured to generate the regenerated interleaver sequence based on the column indexes and computed data.

2 . A turbo decoder according to claim 1 ,
wherein the address generators are configured to read the column indexes from the addressable column index memory; wherein the address generators are configured to compute the computed data for a corresponding turbo decoder engine by permuting row indexes in a same row permuting order as an encoder that encoded the encoded data; and wherein the address generators are configured to combine the column indexes so read and the row indexes so permuted to create the regenerated interleaver sequence.

3 . A turbo decoder according to claim 2 , wherein each of the address generators are operatively coupled to respective row column counters and is configured to select a permutated row.

4 . A turbo decoder according to claim 1 , wherein the address generator is configured to identify out of bounds addresses using the regenerated interleaver sequence.

5 . A turbo decoder according to claim 1 , wherein the loader comprises
a base sequence table; and an intra-row permutations unit operatively coupled to the base sequence table and configured to generate the column indexes.

6 . A turbo decoder according to claim 1 , wherein the loader further comprises an address generator operatively coupled to the addressable column index memory and configured to store a plurality of the column indexes to each individual address location of the addressable column index memory.

7 . A turbo decoder according to claim 1 , wherein each of the address generators are operatively coupled to the addressable column index memory and configured to read a plurality of the column indexes from each individual address location of the addressable column index memory.

8 . A turbo decoder according to claim 1 , further comprising a radio receiver operatively coupled to the loader and configured to receive the encoded data.

9 . A method of decoding encoded data, comprising the steps of:
(a) turbo decoding the encoded data using a regenerated interleaver sequence; (b) loading column indexes based on a predetermined interleaver sequence; (c) storing in an addressable column index memory the column indexes loaded in said step (b) during an input phase of the turbo decoding of said step (a); and (d) generating the regenerated interleaver sequence based on the column indexes stored in said step (c) and computed data.

10 . A method of decoding according to claim 9 , wherein said step (d) of generating the predetermined interleaver sequence comprises the substeps of
(d)(1) reading column indexes from the addressable column index memory; (d)(2) computing the computed data by permuting row indexes in a same row permuting order as an encoder that encoded the encoded data; and (d)(3) combining the column indexes of said step (d)(1) and the row indexes permuted in said step (d)(2) to generate the regenerated interleaver sequence.

11 . A method of decoding according to claim 10 , wherein said step (d)(2) of permuting row indexes comprises the substep of (d)(2)(i) selecting a permutated row using a row column counter.

12 . A method according to claim 9 , wherein said step (d) of generating the regenerated interleaver sequence comprises the substep of (d)(1) identifying out of bounds addresses using the regenerated interleaver sequence generated in said step (d).

13 . A method according to claim 9 , wherein said step (b) of loading generates the column indexes based on at least (b)(1) a base sequence and (b)(1) intra-row permutations.

14 . A method according to claim 9 , wherein said step (b) of loading further comprises an address generator operatively coupled to the addressable column index memory storing a plurality of the column indexes to each individual address location of the addressable column index memory.

15 . A method according to claim 9 , wherein said step (d) of generating the regenerated interleaver sequence comprises the substep of (d)(1) reading a plurality of the column indexes from each individual address location of the addressable column index memory.

16 . A method of decoding, comprising the steps of:
(a) receiving encoded data; (b) turbo decoding said encoded data received in said step (a) using a regenerated interleaver sequence; (c) loading column indexes based on a predetermined interleaver sequence; (d) storing in an addressable column index memory the column indexes loaded in said step (c) during an input phase of the turbo decoding of said step (b); (e) reading column indexes from the addressable column index memory; (f) permuting row indexes in a same row permuting order as an encoder that encoded the encoded data; and (g) combining the column indexes of said step (e) and the row indexes permuted in said step (e) to generate the regenerated interleaver sequence.

17 . A method according to claim 16 , wherein said step (f) of permuting row indexes selects a permutated row using a row column counter.

18 . A method according to claim 16 , wherein said step (f) of permuting row indexes identifies out of bounds addresses using the regenerated interleaver sequence generated in said step (g).

Assignees

• Freescale Semiconductor Inc

Inventors

• Bahary Robert
• Jackowski Eric J

Classifications

• H03M13/2775

  Contention or collision free turbo code internal interleaver · CPC title

• H03M13/2714 Primary

  Turbo interleaver for 3rd generation partnership project [3GPP] universal mobile telecommunications systems [UMTS], e.g. as defined in technical specification TS 25.212 · CPC title

• H03M13/276

  Interleaving address generation · CPC title

• G06F11/1076

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title

• H03M13/2771 Primary

  Internal interleaver for turbo codes (H03M13/2714 and H03M13/2725 take precedence) · CPC title