Interpolator Systems and Methods

Patent metadata

Field	Value
Publication number	US-2016149584-A1
Application number	US-201414551266-A
Country	US
Kind code	A1
Filing date	Nov 24, 2014
Priority date	Nov 24, 2014
Publication date	May 26, 2016
Grant date	—

Abstract

A digital to time converter is disclosed and includes a code logic and an interpolator. The code logic is configured to receive a first phase signal and a second phase signal and generate a select signal according to the first phase signal and the second phase signal. The interpolator has a bank of inverters. The interpolator is configured to generate an interpolator signal based on the select signal and an input signal.

First claim

1 . A digital to time converter comprising:
a code logic configured to receive a first phase signal and a second phase signal and generate a select signal based on the first phase signal and the second phase signal; an interpolator comprising a bank of inverters and configured to generate an interpolator signal based on the select signal and an input signal; and a phase detector configured to generate the input signal based on the first phase signal and the second phase signal.

2 . (canceled)

3 . The converter of claim 1 , wherein the phase detector is configured to generate the input signal as an exclusive OR of the first phase signal and the second phase signal used with a D-flip flop to generate the input signal at its output.

4 . The converter of claim 1 , wherein the phase detector is configured to generate an earlier signal of the first phase signal and the second phase signal as the input signal.

5 . The converter of claim 1 , wherein the code logic is configured to generate a code signal to select one or more varied interpolating inverters of the bank of inverters.

6 . The converter of claim 1 , wherein the code logic is configured to select which inverters of the bank of inverters to use as one or more varied interpolating inverters using dynamic element matching.

7 . The converter of claim 1 , wherein the bank of inverters includes a plurality of inverter cells.

8 . The converter of claim 7 , wherein the plurality of inverter cells each comprise enable logic and a series of transistors, wherein the enable logic is configured to enable the series of transistors and the series of transistors are configured to drive a cell output according to the input signal.

9 . The converter of claim 8 , wherein the enable logic includes an OR gate.

10 . The converter of claim 1 , further comprising an output inverter configured to invert the interpolator signal into a converter output signal.

11 . The converter of claim 1 , further comprising a control unit coupled to the code logic, wherein the control unit specifies a number n of inverters to use for interpolation.

12 . An interpolator cell for a digital to time converter, the interpolator cell comprising:
OR logic configured to receive a code signal and a select signal and to generate an enable signal upon the code signal or the select signal being enabled; and a series of transistors configured to drive a cell output according to an input signal upon the enable signal being generated.

13 . The interpolator cell of claim 12 , wherein the series of transistors include one or more enable transistors configured to disable the cell output on the enable signal not being asserted.

14 . The interpolator cell of claim 12 , wherein the series of transistors include a p-type transistor configured to drive the cell output toward a supply voltage on the input signal being low.

15 . The interpolator cell of claim 12 , wherein the series of transistors include an n-type transistor configured to drive the cell output toward ground on the input signal being high.

16 . The interpolator cell of claim 12 , wherein the input signal is an output of a D flip-flop that receives an exclusive OR of a first phase signal and a second phase signal.

17 . The interpolator cell of claim 12 , further comprising a plurality of interpolator cells coupled to the cell output.

18 . A method of operating a digital to time converter, the method comprising:
providing an earlier of a first phase signal and a second phase signal as an interpolator input signal; selecting varied interpolating inverters of a bank of inverters according to the first phase signal and the second phase signal; interpolating the interpolator input signal using the bank of inverters and the varied interpolating inverters to generate an interpolator output signal based on the interpolator input signal; and converting the interpolator output signal into a converter output signal.

19 . The method of claim 18 , further comprising receiving a first phase signal and a second phase signal at a phase detector.

20 . The method of claim 18 , further comprising interpolating the interpolator output signal using all inverters of the bank of inverters upon the first phase signal and the second phase signal being equal and interpolating the output signal using only the varied interpolating inverters upon the first phase signal and the second phase signal being varied.

Assignees

• Intel Corp

Inventors

• Tertinek Stefan
• Mayer Thomas
• Preyler Peter

Classifications

• H03M1/002

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title

• H03K5/13

  Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals · CPC title

• H03K19/00361

  in field effect transistor circuits · CPC title

• H03M1/661

  Improving the reconstruction of the analogue output signal beyond the resolution of the digital input signal, e.g. by interpolation, by curve-fitting, by smoothing · CPC title

• H03M1/70

  Automatic control for modifying converter range · CPC title