Multi-mode power converter and associated control method

Patent metadata

Field	Value
Publication number	US-2016149494-A1
Application number	US-201514948066-A
Country	US
Kind code	A1
Filing date	Nov 20, 2015
Priority date	Nov 25, 2014
Publication date	May 26, 2016
Grant date	—

Abstract

A multi-mode power converter and associated method for configuring and controlling a multi-mode power converter. The multi-mode power converter may have a boost operation mode and a buck operation mode. A first transistor is coupled between a switching terminal and a ground, and a second transistor and a third transistor are coupled in series between the switching terminal and an output port of the multi-mode power converter. In the buck mode, an on-resistance of the second transistor is regulated to ensure the multi-mode power converter to operate normally in the buck operation mode.

First claim

I/we claim:

1 . A multi-mode power converter comprising:
an input port; an output port; a switching terminal coupled to the input port through an inductive element; a first transistor coupled between the switching terminal and a ground; a second transistor and a third transistor coupled in series between the switching terminal and the output port; wherein the multi-mode power converter has a boost operation mode and a buck operation mode; and wherein in the boost operation mode, the second transistor is ON while the first transistor and the third transistor are switched ON and OFF complementarily, or the second transistor and the third transistor are switched ON and OFF substantially simultaneously while the first transistor and the third transistor are switched ON and OFF complementarily; and wherein in the buck operation mode, the second transistor is ON while the first transistor and the third transistor are switched ON and OFF complementarily, and wherein an on-resistance of the second transistor is regulated to ensure the multi-mode power converter operates normally in the buck operation mode.

2 . The multi-mode power converter of claim 1 , wherein the second transistor and the third transistor has a common connection and respectively has a first body diode and a second body diode, and wherein either an anode of the first body diode and an anode of the second body diode are connected to the common connection or a cathode of the first body diode and a cathode of the second body diode are connected to the common connection.

3 . The multi-mode power converter of claim 2 , wherein the second transistor and the third transistor comprise P channel metal oxide field effect transistors.

4 . The multi-mode power converter of claim 1 , further comprising:
an impedance control circuit having a first terminal, a second terminal and a third terminal, wherein the first terminal is configured to receive a reference signal, the second terminal is coupled to the switching terminal of the multi-mode power converter to sense a switching voltage at the switching terminal and provide a sensed switching voltage, and the third terminal is coupled to the control terminal of the second transistor; and wherein the impedance control circuit is configured to regulate the on-resistance of the second transistor to increase if the sensed switching voltage is lower than the reference signal after a first time period since the moment when the first transistor is switched OFF.

5 . The multi-mode power converter of claim 4 , wherein the impedance control circuit is further configured to regulate the on-resistance of the second transistor to maintain at a first on-resistance during the first time period since the moment when the first transistor is switched OFF.

6 . The multi-mode power converter of claim 4 , wherein the reference signal is equal to or higher than an input voltage provided to the input port of the multi-mode power converter.

7 . The multi-mode power converter of claim 4 , wherein the impedance control circuit comprises:
a comparator configured to receive the reference signal and the sensed switching voltage respectively, and to compare the sensed switching voltage with the reference signal to provide a comparison signal; and a driving circuit configured to receive the comparison signal and to provide a driving signal based on the comparison signal to the control terminal of the second transistor; wherein during the first time period since the moment when the first transistor is switched OFF, the driving signal is configured to maintain the on resistance of the second transistor at a first on-resistance; and wherein after the first time period, if the sensed switching voltage is lower than the reference signal, the driving signal is configured to regulate the on-resistance of the second transistor to increase from the first on-resistance to a second on-resistance.

8 . The multi-mode power converter of claim 4 , wherein the impedance control circuit comprises:
an operational amplifier configured to receive the reference signal and the sensed switching voltage respectively, and to provide a driving signal based on the reference signal and the sensed switching voltage to the control terminal of the second transistor; wherein during the first time period since the moment when the first transistor is switched OFF, the driving signal is configured to maintain the on resistance of the second transistor at a first on-resistance; and wherein after the first time period, if the sensed switching voltage is lower than the reference signal, the driving signal is configured to regulate the on-resistance of the second transistor to increase linearly from the first on-resistance to a second on-resistance.

9 . The multi-mode power converter of claim 4 , wherein the impedance control circuit comprises:
a fourth transistor having a first transistor terminal, a transistor control terminal and a second transistor terminal, wherein the first transistor terminal is configured to receive the reference signal, the transistor control terminal is configured to receive the sensed switching voltage, and the second transistor terminal is coupled to the control terminal of the second transistor; and a resistive circuit having a first terminal coupled to the control terminal of the second transistor, and a second terminal coupled to the ground, and configured to discharge the control terminal of the second transistor; wherein during the first time period since the moment when the first transistor is switched OFF, the fourth transistor is OFF so that the control terminal of the second transistor is forced to have a predetermined control voltage to maintain the on resistance of the second transistor at a first on-resistance; and wherein after the first time period, if the sensed switching voltage is lower than the reference signal, the fourth transistor is ON and configured to charge the control terminal of the second transistor to increase the on-resistance of the second transistor.

10 . The multi-mode power converter of claim 9 , wherein the fourth transistor comprises a depletion mode P channel metal oxide field effect transistor, and wherein the first transistor terminal of the fourth transistor is coupled to the input port to receive an input voltage of the multi-mode power converter, and wherein the input voltage plus an absolute value of a threshold voltage of the fourth transistor is equivalent to the reference signal.

11 . The multi-mode power converter of claim 9 , wherein the fourth transistor comprises an enhancement mode P channel metal oxide field effect transistor or a bipolar PNP transistor; and wherein
the impedance control circuit further comprises an offset circuit configured to provide an offset voltage; and wherein the first transistor terminal of the fourth transistor is coupled to the input port of the multi-mode power converter through the offset circuit, wherein an input voltage provided to the input port plus the offset voltage and minus an absolute value of a threshold voltage of the fourth transistor is equivalent to the reference signal.

12 . The multi-mode power converter of claim 9 , wherein the fourth transistor comprises an enhancement mode P channel metal oxide field effect transistor or a bipolar PNP transistor; and wherein
the impedance control circuit further comprises an offset circuit configured to provide an offset voltage; and wherein the first transistor terminal of the fourth transistor is coupled to the input port of the multi-mode power converter, and the transistor control terminal of the fourth transistor is coupled to the sensed sw

Assignees

• Chengdu Monolithic Power Sys

Inventors

• Li Yike

Classifications

• H03K2017/066

  Maximizing the OFF-resistance instead of minimizing the ON-resistance · CPC title

• H03K2217/0018

  Special modifications or use of the back gate voltage of a FET · CPC title

• H02M3/1582 Primary

  Buck-boost converters (H02M3/1584 takes precedence) · CPC title