Electronic device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-2016149121-A1
Application number	US-201514789841-A
Country	US
Kind code	A1
Filing date	Jul 1, 2015
Priority date	Nov 24, 2014
Publication date	May 26, 2016
Grant date	—

Abstract

This technology provides an electronic device and method for fabricating the same. A method for fabricating an electronic device comprising a transistor includes forming a junction region which is partially amorphized in the semiconductor substrate at a side of the gate; forming a metal layer over the junction region; and performing a heat treatment process on the metal layer into a metal-semiconductor compound layer while crystallizing the junction region.

First claim

What is claimed is:

1 . A method for fabricating an electronic device comprising a transistor, comprising:
providing a semiconductor substrate in which a gate is formed; forming a junction region which is partially amorphized in the semiconductor substrate at a side of the gate; forming a metal layer over the junction region; and performing a heat treatment process on the metal layer to change the metal layer into a metal-semiconductor compound layer while crystallizing the junction region.

2 . The method of claim 1 , wherein the forming of the junction region includes performing an ion implantation process at a temperature at or higher than 450° C.

3 . The method of claim 2 , wherein the performing of the ion implantation process includes implanting Si at a dose of 5×10 14 to 2×10 15 ions/cm 2 and an energy from 1 KeV to 10 KeV.

4 . The method of claim 2 , wherein the performing of the ion implantation process includes implanting C at a dose of 1×10 14 to 2×10 15 ions/cm 2 and an energy from 1 KeV to 20 KeV.

5 . The method of claim 2 , wherein the performing of the ion implantation process includes implanting As at a dose of 1×10 15 to 1×10 16 ions/cm 2 and an energy from 1 KeV to 10 KeV.

6 . The method of claim 2 , wherein performing of the ion implantation process includes implanting P at a dose of 1×10 15 to 2×10 16 ions/cm 2 and an energy from 1 KeV to 10 keV.

7 . The method of claim 1 , wherein the metal-semiconductor compound layer includes a metal silicide.

8 . The method of claim 1 , further comprising:
forming a conductive plug over the metal layer after the forming the metal layer and before the performing the heat treatment process.

9 . The method of claim 8 , wherein the conductive plug includes a metal nitride.

10 . The method of claim 1 , further comprising:
forming a variable resistance element which is electrically coupled to the metal-semiconductor compound layer after the performing the heat treatment process.

11 . The method of claim 10 , wherein the variable resistance element includes two magnetic layers and a tunnel barrier layer interposed between the two magnetic layers.

12 . An electronic device comprising a transistor, wherein the transistor includes:
a semiconductor substrate in which a gate is formed; a junction region formed in the semiconductor substrate at a side of the gate; and a metal-semiconductor compound layer formed over the junction region, and wherein the junction region is in a crystallized state.

13 . The electronic device of claim 12 , further comprising:
a variable resistance element electrically coupled to the metal-semiconductor compound layer.

14 . The electronic device of claim 13 , wherein the variable resistance element includes two magnetic layers and tunnel barrier layer interposed between the two magnetic layers.

15 . The electronic device according to claim 12 , further comprising a microprocessor which includes:
a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor; an operation unit configured to perform an operation based on a result that the control unit decodes the command; and a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed, wherein the transistor is part of at least one of the control unit, the operation unit and the memory unit in the microprocessor.

16 . The electronic device according to claim 12 , further comprising a processor which includes:
a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data; a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit, wherein the transistor is part of at least one of the core unit, the cache memory unit and the bus interface in the processor.

17 . The electronic device according to claim 12 , further comprising a processing system which includes:
a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command; an auxiliary memory device configured to store a program for decoding the command and the information; a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside, wherein the transistor is part of at least one of the processor, the auxiliary memory device, the main memory device and the interface device in the processing system.

18 . The electronic device according to claim 12 , further comprising a data storage system which includes:
a storage device configured to store data and conserve stored data regardless of power supply; a controller configured to control input and output of data to and from the storage device according to a command inputted form an outside; a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside, wherein the transistor is part of at least one of the controller, the storage device, the temporary storage device and the interface in the data storage system.

19 . The electronic device according to claim 12 , further comprising a memory system which includes:
a memory configured to store data and conserve stored data regardless of power supply; a memory controller configured to control input and output of data to and from the memory according to a command inputted form an outside; a buffer memory configured to buffer data exchanged between the memory and the outside; and an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside, wherein the transistor is part of at least one of the memory controller, the memory, the buffer memory and the interface in the memory system.

Assignees

• Sk Hynix Inc

Inventors

• Oh Jae-Geun
• Ryu Choon-Kun
• Lee Hyung-Suk

Classifications

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F13/4068 Primary

  Electrical coupling · CPC title

• G06F3/0646

  Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F12/0802

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title