Thin film transistor and manufacturing method thereof, display device
US-2016181437-A1 · Jun 23, 2016 · US
US2016149018A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016149018-A1 |
| Application number | US-201514685243-A |
| Country | US |
| Kind code | A1 |
| Filing date | Apr 13, 2015 |
| Priority date | Nov 25, 2014 |
| Publication date | May 26, 2016 |
| Grant date | — |
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A method includes defining, on a surface of a material, a plurality of discrete portions of a surface as surface elements having at least one of a laterally-varying size, a laterally-varying shape, and a laterally-varying spacing. A plurality of portions of the material beneath the surface elements are doped with a single quantity of dopant material per element area. The dopant material within the material beneath the surface elements expands to provide a lateral gradient of dopant material in the material beneath the surface elements.
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What is claimed is: 1 . A method comprising: defining, on a surface of a material, a plurality of discrete portions of a surface as surface elements having at least one of a laterally-varying size, a laterally-varying shape, and a laterally-varying spacing; doping a plurality of portions of the material beneath the surface elements with a single quantity of dopant material per element area; and expanding the dopant material within the material beneath the surface to provide a lateral gradient of dopant material in the material beneath the surface. 2 . The method of claim 1 wherein said defining the plurality of discrete portions of the surface comprises defining at least one of a plurality of surface stripes or a plurality of surface matrix cells. 3 . The method of claim 2 wherein said at least one of the plurality of surface stripes or the plurality of surface matrix cells comprise openings in one of an ion beam implantation mask or a diffusion mask, and wherein said doping of the plurality of portions of the material comprises one of implanting or diffusing the dopant material through the openings. 4 . The method of claim 3 wherein said openings define the surface elements onto which said one of a dopant beam or an ion beam to penetrate the surface of the material and implant the dopant material, and wherein said one of the ion beam implantation mask or the diffusion mask screen said one of the dopant beam or the ion beam. 5 . The method of claim 1 wherein the material comprises a semiconductor material. 6 . The method of claim 5 wherein the semiconductor material comprises one of p type semiconductor material or n type semiconductor material. 7 . The method of claim 5 wherein the dopant material comprises one of p type dopant material or n type dopant material. 8 . The method of claim 5 wherein the semiconductor material is included in a semiconductor device. 9 . The method of claim 8 wherein the semiconductor device is one of a resistor, a BJT, a JFET, or a MOSFET. 10 . The method of claim 9 wherein a quantity of dopant material varies along a lateral channel of the semiconductor device. 11 . The method of claim 10 wherein said doping the plurality of portions of the material beneath the surface elements form a plurality of doped regions of the semiconductor device. 12 . The method of claim 11 wherein a quantity of the dopant material in each one of the plurality of doped regions in the lateral channel is defined by a local dopant concentration in said one of the plurality of doped regions. 13 . The method of claim 12 wherein the plurality of doped regions in the lateral channel is formed between a source electrode and a drain electrode of the semiconductor device. 14 . The method of claim 13 wherein a local dopant concentration proximate to the drain electrode of the semiconductor device is greater than a local dopant concentration proximate to the source electrode of the semiconductor device. 15 . The method of claim 14 wherein the local dopant concentration proximate to the drain electrode of the semiconductor device forms a uniform concentration region, and wherein the local dopant concentration proximate to the source electrode of the semiconductor device is reduced with respect to the local dopant concentration proximate to the drain electrode by a radial gradient of dopant towards the source electrode. 16 . The method of claim 15 wherein the semiconductor device is a high voltage switching device, wherein the local dopant concentration proximate to the drain electrode of the semiconductor device is around 25%, and wherein the local dopant concentration proximate to the source electrode is around 5%.
by ion implantation · CPC title
being group IV material · CPC title
within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase · CPC title
into Group IV semiconductors · CPC title
using masks · CPC title
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