Transistor, organic light emitting display having the same, and method of manufacturing organic light emitting display

Patent metadata

Field	Value
Publication number	US-2016148986-A1
Application number	US-201514919666-A
Country	US
Kind code	A1
Filing date	Oct 21, 2015
Priority date	Nov 26, 2014
Publication date	May 26, 2016
Grant date	—

Abstract

A transistor including a polysilicon layer on a base substrate and including a channel region, a first ion doping region, a second ion doping region, the channel region being between the first and second ion doping regions, an average size of the grains in the channel region being greater than that of the grains in the first and second ion doping regions, a first gate electrode insulated from and overlapping the channel region, a second gate electrode insulated from the first gate electrode and overlapping the channel region, an inter-insulating layer on the second gate electrode, a source electrode on the inter-insulating layer and connected to the first ion doping region, and a drain electrode on the inter-insulating layer and connected to the second ion doping region.

First claim

What is claimed is:

1 . A transistor comprising:
a polysilicon layer on a base substrate and comprising a channel region, a first ion doping region, a second ion doping region, the channel region being between the first and second ion doping regions, an average size of the grains in the channel region being greater than that of the grains in the first and second ion doping regions; a first gate electrode insulated from and overlapping the channel region; a second gate electrode insulated from the first gate electrode and overlapping the channel region; an inter-insulating layer on the second gate electrode; a source electrode on the inter-insulating layer and connected to the first ion doping region; and a drain electrode on the inter-insulating layer and connected to the second ion doping region.

2 . The transistor of claim 1 , wherein the grains have an average diameter in a range from about 30 micrometers to about 40 micrometers in a center portion of the polysilicon layer and have an average diameter in a range from about 10 micrometers to about 20 micrometers in an edge portion of the polysilicon layer.

3 . The transistor of claim 1 , wherein the second gate electrode completely covers the first gate electrode when viewed from above the inter-insulating layer.

4 . The transistor of claim 3 ,
wherein the channel region comprises a first channel region overlapping the first and second gate electrodes in a direction in which the first and second ion doping regions are connected to each other, and a second channel region overlapping the second gate electrode and not overlapped with the first gate electrode, and wherein an average size of corresponding ones of the grains in the first channel region is greater than that of corresponding ones of the grains in the second channel region.

5 . The transistor of claim 3 , wherein the first and second gate electrodes define a capacitor charged with electric charges.

6 . The transistor of claim 5 , further comprising:
a first gate insulating layer between the polysilicon layer and the first gate electrode; and a second gate insulating layer between the first gate electrode and the second gate electrode, wherein the first gate insulating layer has a thickness less than a thickness of the second gate insulating layer.

7 . The transistor of claim 6 , further comprising a buffer layer between the base substrate and the polysilicon layer.

8 . An organic light emitting display comprising:
a scan driver configured to apply gate signals to gate lines and to apply light emitting control signals to light emitting lines; a data driver configured to apply data signals to data lines; and an organic light emitting display panel comprising a plurality of pixels, each of the pixels comprising an organic light emitting device and a circuit part configured to control the organic light emitting device, the circuit part comprising a first transistor and a second transistor, the first transistor being configured to output a corresponding data signal applied to a corresponding data line of the data lines in response to a corresponding gate signal applied to a corresponding gate line of the gate lines, and the second transistor being configured to control a driving current flowing through the organic light emitting device, the second transistor comprising: a polysilicon layer on a base substrate and comprising a channel region, a first ion doping region, a second ion doping region, the channel region is being between the first and second ion doping regions, an average size of the grains in the channel region being greater than that of the grains in the first and second ion doping regions; a first gate electrode insulated from and overlapping the channel region; a second gate electrode insulated from the first gate electrode and overlapping the channel region; an inter-insulating layer on the second gate electrode; a source electrode on the inter-insulating layer and connected to the first ion doping region; and a drain electrode on the inter-insulating layer and connected to the second ion doping region.

9 . The organic light emitting display of claim 8 , wherein the grains have an average diameter in a range from about 30 micrometers to about 40 micrometers in a center portion of the polysilicon layer and have an average diameter in a range from about 10 micrometers to about 20 micrometers in an edge portion of the polysilicon layer.

10 . The organic light emitting display of claim 8 , wherein the second gate electrode completely covers the first gate electrode when viewed from above the inter-insulating layer.

11 . The organic light emitting display of claim 10 , wherein the first and second gate electrodes define a capacitor charged with a voltage corresponding to the data signal provided from the first transistor.

12 . The organic light emitting display of claim 11 , further comprising a buffer layer between the base substrate and the polysilicon layer.

13 . A method of manufacturing an organic light emitting display, comprising:
forming an amorphous silicon layer, a first gate electrode insulated from and overlapping the amorphous silicon layer, and a second gate electrode insulated from and overlapping the first gate electrode on a base substrate; irradiating a laser to the amorphous silicon layer from a lower portion of the base substrate to form a polysilicon layer from the amorphous silicon layer; forming an inter-insulating layer on the second gate electrode; ion-doping a portion of the polysilicon layer using the second gate electrode as a mask to form a first ion doping region and a second ion doping region; forming a source electrode connected to the first ion doping region, and a drain electrode connected to the second ion doping region; and forming an organic light emitting device connected to the drain electrode.

14 . The method of claim 13 , wherein the second gate electrode covers the first gate electrode.

15 . The method of claim 14 , wherein the laser comprises an excimer laser.

16 . The method of claim 15 , further comprising:
forming a first gate insulating layer between the polysilicon layer and the first gate electrode; and forming a second gate insulating layer between the first gate electrode and the second gate electrode, wherein the first gate insulating layer has a thickness less than a thickness of the second gate insulating layer.

17 . The method of claim 16 , further comprising forming a buffer layer between the base substrate and the polysilicon layer.

Assignees

• Samsung Display Co Ltd

Inventors

• Lee Kyoungwon
• Khang Yoonho
• Cha Myounggeun
• Shin Youngki
• Jeong Woonghee

Classifications

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6745

  Polycrystalline or microcrystalline silicon · CPC title

• H10D30/6733

  Multi-gate TFTs · CPC title