Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2016148948-A1
Application number	US-201514698571-A
Country	US
Kind code	A1
Filing date	Apr 28, 2015
Priority date	Nov 21, 2014
Publication date	May 26, 2016
Grant date	—

Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a core insulating film, a channel film surrounding the core insulating film and extending to a higher level than an upper surface of the core insulating film to have a first end of the channel film exposed over the core insulating film, a channel pad formed over an inner wall of the first end of the channel film exposed over the core insulating film, and a contact plug coupled to the channel pad.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a core insulating film; a channel film surrounding the core insulating film and extending to a higher level than an upper surface of the core insulating film to have a first end of the channel film exposed over the core insulating film; a channel pad formed over an inner wall of the first end of the channel film exposed over the core Insulating film; and a contact plug coupled to the channel pad.

2 . The semiconductor device of claim 1 , further comprising:
a stack including interlayer insulating films and conductive patterns and surrounding the channel film, wherein the interlayer insulating films and the conductive patterns are alternately stacked over each other; an upper insulating film formed over the stack; a first contact hole penetrating through the upper insulating film and overlapping the channel pad; and a second contact hole extending from the first contact hole to the core insulating film and surrounded by the first end of the channel film, wherein the contact plug fills the first contact hole.

3 . The semiconductor device of claim 2 , wherein the channel pad is formed in a tube shape, and
wherein the contact plug is T-shaped and further fills the second contact hole.

4 . The semiconductor device of claim 2 , wherein the channel pad extends to fill the second contact hole, and
wherein the contact plug is formed over the channel pad.

5 . The semiconductor device of claim 2 , wherein the conductive patterns comprise:
a select line formed at substantially the same level as the channel pad; and word lines formed at a lower level than the channel pad.

6 . The semiconductor device of claim 1 , wherein the channel pad comprises a doped silicon film.

7 . The semiconductor device of claim 1 , wherein the channel film comprises an undoped silicon film.

8 . The semiconductor device of claim 1 , wherein the first end of the channel film has a narrower width than the remaining portion of the channel film which is not exposed over the core insulating film.

9 . The semiconductor device of claim 2 , further comprising:
a substrate provided under the stack and having a source region connected to a second end of the channel film; and a bit line connected to the contact plug.

10 . A semiconductor device, comprising:
a pipe gate; a drain-side stacked structure formed over the pipe gate and including first interlayer insulating films and first conductive patterns, wherein the first interlayer insulating films and the first conductive patterns are alternately stacked; a source-side stacked structure formed over the pipe gate and including second interlayer insulating films and second conductive patterns, wherein the second interlayer insulating films and the second conductive patterns are alternately stacked; a first core insulating film penetrating the drain-side stacked structure; a second core insulating film penetrating the source-side stacked structure; a third core insulating film connecting the first core insulating film and the second core insulating film and formed in the pipe gate; a channel film surrounding the first, the second, and the third core insulating films, wherein the channel film extends to a higher level than an upper surface of the first core insulating film to have a first end of the channel film exposed over the first core insulating film, wherein the channel film extends to a higher level than an upper surface of the second core insulating film to have a second end of the channel film exposed over the second core insulating film; a first channel pad formed over an inner wall of the first end of the channel film; a second channel pad formed over an inner wall of the second end of the channel film; and first and second contact plugs coupled to the first and the second channel pads, respectively.

11 . The semiconductor device of claim 10 , wherein the first and second channel pads are in a tube shape with a hollow center and formed over the inner walls of the first and second ends of the channel film, respectively,
wherein the first contact plug is in a T-shape so that an upper portion has a wider width than a lower portion, wherein the lower portion of the first contact plug fills the hollow center of the first channel pad, wherein the second contact plug is in a T-shape so that an upper portion has a wider width than a lower portion, and wherein the lower portion of the second contact plug fills the hollow center of the second channel pad.

12 . The semiconductor device of claim 10 , wherein the first channel pad is in a pillar shape with no hollow center and fills the region defined by the first end of the channel film and the first core insulating film,
wherein the second channel pad is in a pillar shape with no hollow center and fills the region defined by the second end of the channel film and the second core insulating film, wherein the first contact plug is formed at a higher level than the first channel pad, and wherein the second contact plug is formed at a higher level than the second channel pad.

13 . A method of manufacturing a semiconductor device, comprising:
forming a stack in which first material films and second material films are alternately and repeatedly stacked; forming a channel hole penetrating the stack; forming a channel film over a sidewall of the channel hole; forming a core insulating film filling the channel hole opened by the channel film; forming an upper insulating film over the core insulating film and over the channel film; forming a first contact hole by patterning the upper insulating film; forming a second contact hole extending from the first contact hole by patterning the core insulating film to expose a first end of the channel film; forming a channel pad over an inner wall of the first end of the channel film; and forming a contact plug coupled to the channel pad by filling the first contact hole.

14 . The method of manufacturing the semiconductor device of claim 13 , wherein the upper insulating film is in contact with an upper surface of the core insulating film.

15 . The method of manufacturing the semiconductor device of claim 13 , wherein the forming of the first contact hole and the forming of the second contact hole are performed using the same etching process.

16 . The method of manufacturing the semiconductor device of claim 13 , wherein the first end of the channel film is has a smaller width than the remaining portion of the channel film protected by the core insulating film.

17 . The method of manufacturing the semiconductor device of claim 13 , wherein the forming of the channel pad comprises a selective growth method.

18 . The method of manufacturing the semiconductor device of claim 13 , wherein the channel pad is in a tube shape with a hollow center, and
wherein the contact plug extends to the first contact hole by filling the hollow center of the channel pad.

19 . The method of manufacturing the semiconductor device of claim 13 , wherein the channel pad is in a pillar shape and fills the second contact hole, and
wherein the contact plug is formed at a higher level than the channel pad.

20 . The method of manufacturing the semiconductor device of claim 13 , wherein the channel pad includes a doped silicon film.

Assignees

• Sk Hynix Inc

Inventors

• Kim Tae Kyung

Classifications

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L21/76897

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic