Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2016148932-A1
Application number	US-201514885308-A
Country	US
Kind code	A1
Filing date	Oct 16, 2015
Priority date	Nov 21, 2014
Publication date	May 26, 2016
Grant date	—

Abstract

A semiconductor device including an insulating film in a first region of a semiconductor substrate; a first impurity region and a second impurity region of a first conductivity type, each of the regions including a part located deeper than the insulating film in contact with each other, and the insulating film being sandwiched by the first and second impurity regions in planar view in the first region of the semiconductor substrate; a metal silicide film on the first impurity region and in Schottky junction with the first impurity region; a first impurity of the first impurity region having a peak of a concentration profile deeper than a bottom of the insulating film; a second impurity of the second impurity region having a concentration higher than a concentration of the first impurity in a part of the first impurity region shallower than the bottom of the insulating film.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
an insulating film in a first region of a semiconductor substrate; a first impurity region of a first conductivity type and a second impurity region of the first conductivity type, each of the first impurity region and the second impurity region including a part located deeper than the insulating film, and the insulating film being sandwiched by the first impurity region and the second impurity region in planar view in the first region of the semiconductor substrate; and a metal silicide film on the first impurity region and in Schottky junction with the first impurity region, wherein the first impurity region contains a first impurity of the first conductivity type such that a peak of a concentration profile is deeper than a bottom of the insulating film, the second impurity region contains a second impurity of the first conductivity type, a concentration of the second impurity in the second impurity region being higher than a concentration of the first impurity in a part of the first impurity region shallower than the bottom of the insulating film, and the first impurity region and the second impurity region are in contact with each other at a position deeper than the bottom of the insulating film.

2 . The semiconductor device according to claim 1 , wherein a concentration of the first impurity in a part of the first impurity region deeper than the bottom of the insulating film is higher than the concentration of the second impurity in the second impurity region.

3 . The semiconductor device according to claim 1 , further comprising a third impurity region of a second conductivity type different from the first conductivity type, the third impurity region being locally formed between the first impurity region and the metal silicide film.

4 . The semiconductor device according to claim 3 , wherein the third impurity region is in contact with the insulating film.

5 . The semiconductor device according to claim 1 , further comprising:
a gate electrode in a second region of the semiconductor substrate; and a fourth impurity region of the first conductivity type below the gate electrode, wherein a concentration profile of a third impurity of the first conductivity type in the fourth impurity region is substantially identical to a part of the concentration profile of the first impurity in the first impurity region.

6 . The semiconductor device according to claim 1 , further comprising:
a fourth impurity region of the first conductivity type in a second region of the semiconductor substrate; a semiconductor layer on the fourth impurity region; and a gate electrode formed on the semiconductor layer in the second region.

7 . A method of manufacturing a semiconductor device, comprising:
forming a first impurity region of a first conductivity type in a first region of a semiconductor substrate; forming a second impurity region of the first conductivity type in contact with the first impurity region in the first region of the semiconductor substrate; forming an insulating film that separates a surface of the first impurity region and a surface of the second impurity region to be shallower than the first impurity region and the second impurity region, and such that the first impurity region and the second impurity region are in contact with each other at a position deeper than a bottom of the insulating film in the first region of the semiconductor substrate; and forming a metal silicide film on the first impurity region and in Schottky junction with the first impurity region, wherein a first impurity of the first conductivity type is doped such that a peak of a concentration profile is deeper than the bottom of the insulating film in the forming the first impurity region, and a second impurity of the first conductivity type is doped such that a concentration of the second impurity in the second impurity region is higher than a concentration of the first impurity in a part of the first impurity region shallower than the bottom of the insulating film.

8 . The method according to claim 7 , wherein a concentration of the first impurity in a part of the first impurity region deeper than the bottom of the insulating film is higher than the concentration of the second impurity in the second impurity region.

9 . The method according to claim 7 , further comprising locally forming a third impurity region of a second conductivity type different from the first conductivity type between the first impurity region and the metal silicide film.

10 . The method according to claim 9 , wherein the third impurity region is in contact with the insulating film.

11 . The method according to claim 7 , further comprising:
forming a fourth impurity region of the first conductivity type in a second region of the semiconductor substrate contemporaneously with a time period in which the first impurity region is formed; and forming a gate electrode above the fourth impurity region of the semiconductor substrate, wherein a concentration profile of a third impurity of the first conductivity type in the fourth impurity region is substantially identical to the concentration profile of the first impurity in the first impurity region.

12 . The method according to claim 7 , further comprising:
forming a fourth impurity region of the first conductivity type in a second region of the semiconductor substrate contemporaneously with a time period in which the first impurity region is formed; forming a semiconductor layer on the semiconductor substrate after the forming the fourth impurity region and before the forming the insulating film; and forming a gate electrode on the semiconductor layer in the second region of the semiconductor substrate.

Assignees

• Fujitsu Semiconductor Ltd

Inventors

• Fujita Kazushi
• Ema Taiji
• Yasuda Makoto
• Hori Mitsuaki

Classifications

• H10D8/051

  of Schottky diodes · CPC title

• H10D8/045

  of PN junction diodes · CPC title

• H10D89/611

  using diodes as protective elements · CPC title

• H10D84/859

  comprising both N-type and P-type wells, e.g. twin-tub · CPC title

• H10D84/0191

  Manufacturing their doped wells · CPC title