Defect Logging in Nonvolatile Memory

Patent metadata

Field	Value
Publication number	US-2016148708-A1
Application number	US-201414550290-A
Country	US
Kind code	A1
Filing date	Nov 21, 2014
Priority date	Nov 21, 2014
Publication date	May 26, 2016
Grant date	—

Abstract

A method of operating a nonvolatile memory block includes reading data from physical units in the block and determining individual error rates for data from the physical units. The error rate data is stored. This is repeated over multiple iterations and aggregated stored error rates are used to identify bad physical units in the block.

First claim

It is claimed:

1 . A method of operating an individually erasable block in a nonvolatile memory system comprising:
(a) writing data in a plurality of physical units in the individually erasable block; (b) subsequently, reading the data from the plurality of physical units in the individually erasable block and determining individual error rates for data from the plurality of physical units; (c) erasing the individually erasable block; (d) storing the individual error rates; (e) subsequently repeating steps (a)-(d) in one or more additional iterations; and (f) identifying one or more physical units in the individually erasable block as bad and not for subsequent storage of user data, the bad physical units identified by aggregating stored individual error rates from two or more iterations of steps (a)-(d).

2 . The method of claim 1 wherein an individual physical unit stores an amount of data that is equal to the amount of data that is individually encoded and decoded by an Error Correction Code (ECC) scheme of the nonvolatile memory system.

3 . The method of claim 1 wherein the individual error rates are stored only for physical units that have error rates that exceed a threshold value.

4 . The method of claim 1 wherein step (d) storing the individual error rates includes writing the individual error rates in the individually erasable block after step (c) erasing the individually erasable block.

5 . The method of claim 1 further comprising: (g) identifying one or more additional physical units in the individually erasable block as suspect units by aggregating stored individual error rates of two or more iterations of steps (a)-(d).

6 . The method of claim 5 further comprising performing testing on the suspect units, the testing including writing test data and reading the test data.

7 . The method of claim 5 further comprising, prior to folding data of the individually erasable block with one or more other individually erasable blocks, determining if the one or more other individually erasable blocks contain suspect units and ensuring that uncorrected data from a suspect unit in the individually erasable block is not folded together with uncorrected data from a suspect unit in the one or more other individually erasable block.

8 . The method of claim 7 wherein the ensuring comprises performing Error Correction Code (ECC) correction on at least some of the data from suspect units prior to folding.

9 . The method of claim 1 wherein the nonvolatile memory system comprises a plurality of individually erasable blocks and the individually erasable block is selected for step (d) storing the individual error rates, in response to a determination that the individually erasable block has a block error rate above a limit.

10 . The method of claim 9 wherein step (d) storing the individual error rates, is not performed for any physical units in other individually erasable blocks of the plurality of individually erasable blocks that have error rates below the limit.

11 . A method of operating a plurality of monitored blocks in a nonvolatile memory system comprising:
maintaining individual error maps for each of the plurality of monitored blocks; identifying two or more monitored blocks of the plurality of monitored blocks for a block folding operation; analyzing individual error maps for the two or more monitored blocks to select a block folding scheme according to the individual error maps from two or more block folding schemes including at least: (a) on-chip block folding without Error Correction Code (ECC) correction of data and (b) off-chip block folding with ECC correction; and subsequently performing the block folding operation using the selected block folding scheme.

12 . The method of claim 11 wherein on-chip block folding without ECC correction is selected in response to determining that errors for the two or more blocks are not overlapping and that overall error rates of the two or more blocks are below a threshold.

13 . The method of claim 11 wherein off-chip block folding with ECC correction is selected in response to determining that errors for the two or more monitored blocks overlap or that overall error rates are above a threshold.

14 . The method of claim 13 wherein the error maps for the two or more monitored blocks are updated according to results of the ECC correction.

15 . The method of claim 11 wherein the nonvolatile memory system includes unmonitored blocks for which no individual error maps are maintained.

16 . The method of claim 15 further comprising: designating a previously unmonitored block as a monitored block in response to a determination that a number of errors in the previously unmonitored block exceeds a predetermined number.

17 . The method of claim 11 wherein maintaining the individual error maps includes accumulating error data for the plurality of monitored blocks over a plurality of write-erase cycles and storing each of the individual error maps in corresponding monitored blocks.

18 . A block erasable nonvolatile memory system comprising:
a plurality of monitored blocks having error rates above a threshold; an individual monitored block containing an error log that records error data for a plurality of physical areas of the individual monitored block for a plurality of write-erase cycles of the individual monitored block; and a persistent error identification circuit that identifies physically defective areas of the individual monitored block from the error log.

19 . The block erasable nonvolatile memory system of claim 18 wherein the error log contains entries for only physical areas of the block that have error rates above a threshold.

20 . The block erasable nonvolatile memory system of claim 18 further comprising a plurality of unmonitored blocks having error rates below the threshold.

21 . The block erasable nonvolatile memory system of claim 18 further comprising a testing circuit that performs testing on physical areas of the block for which the error log indicates a high error rate.

22 . The block erasable nonvolatile memory system of claim 18 further comprising an Error Correction Code (ECC) circuit, and wherein data is folded from two or more source blocks into a destination block either using or not using the ECC circuit according to a determination based on data in the error logs of the source blocks.

Assignees

• Sandisk Technologies Inc

Inventors

• Tuers Daniel
• Manohar Abhijeet

Classifications

• G11C16/00

  Erasable programmable read-only memories (G11C14/00 takes precedence) · CPC title

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title

• G11C29/38 Primary

  Response verification devices · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title