Magnetic tunnel junction resistance comparison based physical unclonable function

Patent metadata

Field	Value
Publication number	US-2016148666-A1
Application number	US-201414555434-A
Country	US
Kind code	A1
Filing date	Nov 26, 2014
Priority date	Nov 26, 2014
Publication date	May 26, 2016
Grant date	—

Abstract

A method includes coupling a first magnetic tunnel junction (MTJ) element and a second MTJ element to a comparison circuit. The method also includes comparing, at the comparison circuit, a first resistance of the first MTJ element to a second resistance of the second MTJ element. The method further includes generating a first physical unclonable function (PUF) output bit based on a result of comparing the first resistance to the second resistance.

First claim

What is claimed is:

1 . A method comprising:
coupling a first magnetic tunnel junction (MTJ) element and a second MTJ element to a comparison circuit; comparing, at the comparison circuit, a first resistance of the first MTJ element to a second resistance of the second MTJ element; and generating a first physical unclonable function (PUF) output bit based on a result of comparing the first resistance to the second resistance.

2 . The method of claim 1 , wherein the first MTJ element and the second MTJ element are non-adjacent MTJ elements.

3 . The method of claim 1 , further comprising:
coupling a third MTJ element to the comparison circuit; comparing, at the comparison circuit, the first resistance of the first MTJ element to a third resistance of the third MTJ element; and generating a second PUF output bit based on a result of comparing the first resistance to the third resistance.

4 . The method of claim 3 , wherein the first MTJ element and the third MTJ element are non-adjacent MTJ elements.

5 . The method of claim 1 , wherein the first PUF output bit is used as a product identifier.

6 . The method of claim 1 , further comprising programming the first MTJ element and the second MTJ element to the same state prior to comparing the first resistance to the second resistance.

7 . The method of claim 6 , wherein the state is a parallel state or an anti-parallel state.

8 . The method of claim 1 , further comprising:
coupling a third MTJ element having a third resistance in series with the first MTJ element and coupling a fourth MTJ element having a fourth resistance in series with the second MTJ element; comparing, at the comparison circuit, a first sum of the first resistance and the third resistance to a second sum of the second resistance and the fourth resistance; and generating a second PUF output bit based on a result of comparing the first sum to the second sum.

9 . An apparatus comprising:
a first selection circuit having a first input coupled to a first magnetic tunnel junction (MTJ) element and having a second input coupled to a second MTJ element; a second selection circuit having a first input coupled to the first MTJ element and having a second input coupled to the second MTJ element; a comparison circuit configured to:
compare a first resistance of the first MTJ element to a second resistance of the second MTJ element, wherein the first MTJ element is coupled to the comparison circuit via one of the first selection circuit or the second selection circuit, and wherein the second MTJ element is coupled to the comparison circuit via the other of the first selection circuit or the second selection circuit; and
generate a first physical unclonable function (PUF) output bit based on a result of comparing the first resistance to the second resistance.

10 . The apparatus of claim 9 , wherein the first MTJ element and the second MTJ element are non-adjacent MTJ elements.

11 . The apparatus of claim 9 , wherein the first selection circuit has a third input coupled to a third MTJ element, wherein the second selection circuit has a third input coupled to the third MTJ element, and wherein the comparison circuit is further configured to:
compare the first resistance of the first MTJ element to a third resistance of the third MTJ element, wherein the first MTJ element is coupled to the comparison circuit via one of the first selection circuit or the second selection circuit, and wherein the third MTJ element is coupled to the comparison circuit via the other of the first selection circuit or the second selection circuit; and generate a second PUF output bit based on a result of comparing the first resistance to the third resistance.

12 . The apparatus of claim 11 , wherein the first MTJ element and the third MTJ element are non-adjacent MTJ elements.

13 . The apparatus of claim 9 , wherein the first PUF output bit is used as a product identifier.

14 . The apparatus of claim 9 , further comprising a processor configured to program the first MTJ element and the second MTJ element to an identical state.

15 . The apparatus of claim 18 , wherein the state is a parallel state or an anti-parallel state.

16 . The apparatus of claim 9 , further comprising:
a third selection circuit configured to couple a third MTJ element having a third resistance in series with the first MTJ element; and a fourth selection circuit configured to couple a fourth MTJ element having a fourth resistance in series with the second MTJ element, wherein the comparison circuit is further configured to:
compare a first sum of the first resistance and the third resistance to a second sum of the second resistance and the fourth resistance; and
generate a second PUF output bit based on a result of comparing the first sum to the second sum.

17 . A non-transitory computer-readable medium comprising instructions that, when executed by a processor, cause the processor to:
couple a first magnetic tunnel junction (MTJ) element and a second MTJ element to a comparison circuit; compare, at the comparison circuit, a first resistance of the first MTJ element to a second resistance of the second MTJ element; and generate a first physical unclonable function (PUF) output bit based on a result of comparing the first resistance to the second resistance.

18 . The non-transitory computer-readable medium of claim 17 , wherein the first MTJ element and the second MTJ element are non-adjacent MTJ elements.

19 . The non-transitory computer-readable medium of claim 17 , further comprising instructions that, when executed by the processor, cause the processor to:
couple a third MTJ element to the comparison circuit; compare, at the comparison circuit, the first resistance of the first MTJ element to a third resistance of the third MTJ element; and generate a second PUF output bit based on a result of comparing the first resistance to the third resistance.

20 . The non-transitory computer-readable medium of claim 19 , wherein the first MTJ element and the third MTJ element are non-adjacent MTJ elements.

21 . The non-transitory computer-readable medium of claim 17 , wherein the first PUF output bit is used as a product identifier.

22 . The non-transitory computer-readable medium of claim 17 , further comprising instructions that, when executed by the processor, cause the processor to program the first MTJ element and the second MTJ element to an identical state.

23 . The non-transitory computer-readable medium of claim 22 , wherein the state is a parallel state or an anti-parallel state.

24 . The non-transitory computer-readable medium of claim 17 , further comprising instructions that, when executed by the processor, cause the processor to:
couple a third MTJ element having a third resistance in series with the first MTJ element and couple a fourth MTJ element having a fourth resistance in series with the second MTJ element; compare, at the comparison circuit, a first sum of the first resistance and the third resistance to a second sum of the second resistance and the fourth resistance; and generate a second PUF output bit based on a result of comparing the first sum to the second sum.

25 . An apparatus comprising:
means for selecting having a first input coupled to a first magnetic tunnel junction (MTJ) element and having a second input coupled to a second MTJ element; and means fo

Assignees

• Qualcomm Inc

Inventors

• Rosenberg Brian Marc
• Zhu Xiaochun
• Guo Xu

Classifications

• G09C1/00

  Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) · CPC title

• G11C16/20

  Initialising; Data preset; Chip identification · CPC title

• H04L9/3278

  using physically unclonable functions [PUF] · CPC title

• G11C11/1695

  Protection circuits or methods · CPC title

• H04L9/0866

  involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics · CPC title