Test method and test device for line defect of display panel

Patent metadata

Field	Value
Publication number	US-2016148587-A1
Application number	US-201314389031-A
Country	US
Kind code	A1
Filing date	Sep 17, 2013
Priority date	May 30, 2013
Publication date	May 26, 2016
Grant date	—

Abstract

A test method for line defect in a display panel ( 10 ) comprises: inputting a first ON signal and a first OFF signal into odd rows of gate scanning lines (GE 12 ) and even rows of gate scanning lines (GS 13 ) of the display panel ( 10 ) respectively, to turn on transistors controlled by the odd rows of gate scanning lines (GE 12 ), and turn off transistors controlled by the even rows of gate scanning lines (GS 13 ), thereby obtaining a first test image; inputting a second OFF signal and a second ON signal into the odd rows of gate scanning lines (GE 12 ) and even rows of gate scanning lines (GS 13 ) of the display panel ( 10 ) respectively, to turn off the transistors controlled by the odd rows of gate scanning lines (GE 12 ), and turn on the transistors controlled by the even rows of gate scanning lines (GE 13 ), thereby obtaining a second test image; comparing the first test image with the second test image to determine that line display defect appearing in the first test image or the second test image are true display defect. Also is disclosed a test device for line defect in a display panel ( 10 ). This method allows the test result to approach the lighting test result under module signal input state and can detect true defect of the display panel ( 10 ).

First claim

1 . A test method for line defect in a display panel comprising a plurality rows of gate lines and a plurality columns of data lines intersecting each other to thereby define pixel units arranged in an array, each pixel unit comprising a transistor serving as a switching element, switching state of the transistor being controlled by a corresponding gate line, the method comprising:
inputting a first ON signal and a first OFF signal into odd rows of gate scanning lines and even rows of gate scanning lines of the display panel respectively, to turn on transistors controlled by the odd rows of gate scanning lines, and turn off transistors controlled by the even rows of gate scanning lines, thereby obtaining a first test image of the display panel; inputting a second OFF signal and a second ON signal into the odd rows of gate scanning lines and the even rows of gate scanning lines of the display panel respectively, to turn off the transistors controlled by the odd rows of gate scanning lines, and turn on the transistors controlled by the even rows of gate scanning lines, thereby obtaining a second test image of the display panel; and comparing the first test image with the second test image to determine that line display defect appearing in the first test image or the second test image is true display defect; wherein the method further comprises: inputting a third ON signal into both the odd rows of gate scanning lines and the even rows of gate scanning lines of the display panel, to turn on the transistors controlled by both the odd rows and the even rows of gate scanning lines, thereby obtaining a third test image of the display panel; comparing the first test image and the second test image with the third test image to determine that line display defects appearing in the third test image but not in the first test image and the second test image are false display defects.

2 . (canceled)

3 . The method of claim 1 , wherein the first ON signal and the second ON signal are same; and the first OFF signal and the second OFF signal are same.

4 . The method of claim 1 , wherein all of the first ON signal, the second ON signal and the third ON signal are same.

5 . The method of claim 1 , wherein the first ON signal, the second ON signal and/or the third ON signal are high level signals, and the first OFF signal and/or the second OFF signal are low level signals.

6 . The method of claim 1 , wherein the first ON signal, the second ON signal and/or the third ON signal are alternate current signals or direct current signals, and the first OFF signal and/or the second OFF signal are direct current signals.

7 . The method of claim 6 , wherein when the first ON signal, the second ON signal and/or the third ON signal are direct current signals, a magnitude range of voltages is from 15 voltage to 28 voltage; when the first OFF signal and/or the second OFF signal are direct current signals, a magnitude range of voltages is from −10 voltage to −6 voltage.

8 . The method of claim 6 , wherein the first ON signal, the second ON signal and/or the third ON signal are direct current signals of 21.5 V or alternate current signals of −7.8 V to 21.5 V; and the first OFF signal and/or the second OFF signal are direct current signals of −7.8 V.

9 . A test device for the method of claim 1 , comprising:
a signal output unit configured to input a first ON signal and a first OFF signal into odd rows of gate scanning lines and even rows of gate scanning lines of a display panel in a first stage to turn on transistors controlled by the odd rows of gate scanning lines and turn off the transistors controlled by the even rows of gate scanning lines, thereby obtaining a first test image of the display panel; and input a second OFF signal and a second ON signal into the odd rows of gate scanning lines and the even rows of gate scanning lines of the display panel in a second stage to turn off the transistors controlled by the odd rows of gate scanning lines and turn on the transistors controlled by the even rows of gate scanning lines, thereby obtaining a second test image of the display panel; a determination unit configured to judge a line display defect in the first test image and the second test image to determine that the line display defect appearing in the first test image or the second test image is a true display defect; and a result output unit configured to output a determination result of the determination unit; wherein the signal output unit is further configured to input a third ON signal into both the odd rows of gate scanning lines and the even rows of gate scanning lines of the display panel in a third stage, to turn on the transistors controlled by the both the odd rows and the even rows of gate scanning lines, thereby obtaining a third test image of the display panel.

10 . (canceled)

11 . The test device of claim 10 , wherein the determination unit is further configured to compare the third test image with the first test image and the second test image to determine that line display defects appearing in the third test image but not in the first test image and the second test image are false display defects.

Assignees

• Boe Technology Group Co Ltd
• Hefei Boe Optoelectronics Tech

Inventors

• Li Ming
• Jang Jongseok
• Kim Yong Sub
• Liu Xiaotao

Classifications

• G09G3/3677

  suitable for active matrices only · CPC title

• G06T7/001

  using an image reference approach · CPC title

• G09G2310/0202

  Addressing of scan or signal lines · CPC title

• G06T2207/30121

  CRT, LCD or plasma display · CPC title

• G09G3/3648 Primary

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title