Apparatus and method for efficient frame-to-frame coherency exploitation for sort-last architectures

US2016148339A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016148339-A1
Application numberUS-201414549430-A
CountryUS
Kind codeA1
Filing dateNov 20, 2014
Priority dateNov 20, 2014
Publication dateMay 26, 2016
Grant date

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  1. Title

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Abstract

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An apparatus and method are described for the frame-to-frame coherency algorithm for sort-last architecture. In one embodiment of the invention, if a tile of pixels is covered completely by one triangle from a static draw call in one frame, then that tile is marked with that draw call's identifier. For the next frame, if the same static draw call is drawn, the same tile will be visited, and if the draw call's fragment passes for all pixels, it indicates that tile will contain exactly the same pixel color values as the previous frame. Hence, there is no requirement to run the pixel shader for the tile of pixels, and the color values of the tile can instead be reused from the previous frame.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method comprising: storing an identifier associated with a tile of pixels; determining whether the tile of pixels is covered completely by a first static draw call in a first frame; and setting the identifier associated with the tile of pixels to an identifier associated with the first static draw call in response to a determination that the tile of pixels is covered completely by the triangle from the first static draw call in the first frame. 2 . The method of claim 1 , wherein determining whether the tile of pixels is covered completely by the first static draw call in the first frame comprises determining whether the tile of pixels is covered completely by a triangle from the first static draw call in the first frame. 3 . The method of claim 1 , further comprising: determining whether all fragments of the first static draw call pass a depth test; and setting the identifier associated with the tile of pixels to the identifier associated with the first static draw call in response to the determination that the tile of pixels is covered completely by the first static draw call in the first frame and a determination that all fragments of the first static draw call pass the depth test. 4 . The method of claim 3 , further comprising: determining, in a second frame, whether an identifier of a second static draw call matches the identifier associated with the tile of pixels; and reusing pixel color values of the tile of pixels in the first frame for the pixel color values of the tile of pixels in the second frame. 5 . The method of claim 4 , wherein the identifier associated with the tile of pixels comprises a N-bit number, and wherein the N-bit number comprises one bit combination to indicate that reusing the pixel color values for the tile of pixels in the first frame for the pixel color values for the tile of pixels in the second frame is not possible. 6 . The method of claim 5 , wherein the one bit combination is 2 N −1. 7 . The method of claim 4 , wherein the first static draw call and the second static draw call have one or more of the same input, state, uniform, texture, geometry, and state vector. 8 . The method of claim 3 , wherein the first static draw call and the second static draw call are marked by a user. 9 . At least one computer readable storage medium comprising a set of instructions which, when executed by a computing device, cause the computing device to: initializing a coverage mask comprising a plurality of bits, each bit associated with a respective one of a plurality of samples of a tile; for each of one or more triangles of a first static draw call in a first frame, setting the bit associated with the respective one sample when the respective one sample has been overwritten; and setting an identifier of the tile to an identifier of the first static draw call when all bits of the coverage mask have been set. 10 . The medium of claim 9 , wherein the coverage mask is stored in a cache comprising a plurality of cache lines. 11 . The medium of claim 9 , wherein an eviction policy of the cache comprises evicting a least recently used cache line or evict a cache line comprising a coverage mask with fewest number of set bits. 12 . The medium of claim 9 , further comprising: determining whether all samples of the tile call pass a depth test; and setting the identifier of the tile to an identifier of the first static draw call when all bits of the coverage mask have been set and when all samples of the tile call pass the depth test. 13 . The medium of claim 12 , further comprising: determining, in a second frame, whether an identifier of a second static draw call matches the identifier of the tile; and reusing pixel color values of the tile in the first frame for the pixel color values of the tile in the second frame. 14 . The medium of claim 12 , wherein the identifier of the tile comprises a N-bit number, and wherein the N-bit number comprises one bit combination to indicate that reusing pixel color values of the tile in the first frame for the pixel color values of the tile in the second frame is not possible. 15 . The medium of claim 14 , wherein the one bit combination is 2 N −1. 16 . The medium of claim 13 , wherein the first static draw call and the second static draw call have one or more of the same input, state, uniform, texture, geometry, and state vector. 17 . The medium of claim 13 , wherein the first static draw call and the second static draw call are marked by a user. 18 . An apparatus comprising: a graphics processing engine to: store an identifier associated with a tile of pixels; determine whether the tile of pixels is covered completely by a first static draw call in a first frame; and set the identifier associated with the tile of pixels to an identifier associated with the first static draw call in response to a determination that the tile of pixels is covered completely by the first static draw call in the first frame. 19 . The apparatus of claim 18 , wherein the graphics processing engine to determine whether the tile of pixels is covered completely by the first static draw call in the first frame is to determine whether the tile of pixels is covered completely by a triangle from the first static draw call in the first frame. 20 . The apparatus of claim 18 , wherein the graphics processing engine is further to: determine whether all fragments of the first static draw call pass a depth test; and set the identifier associated with the tile of pixels to the identifier associated with the first static draw call in response to the determination that the tile of pixels is covered completely by the first static draw call in the first frame and a determination that all fragments of the first static draw call pass the depth test. 21 . The apparatus of claim 19 , wherein the graphics processing engine is further to: determine, in a second frame, whether an identifier of a second static draw call matches the identifier associated with the tile of pixels; and reuse pixel color values of the tile of pixels in the first frame for the pixel color values of the tile of pixels in the second frame. 22 . The apparatus of claim 18 , wherein the identifier of the tile comprises a N-bit number, and wherein the N-bit number comprises one bit combination to indicate that reusing pixel color values of the tile of pixels in the first frame for the pixel color values of the tile of pixels in the second frame is not possible.

Assignees

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Classifications

  • Tiling · CPC title

  • G06T1/60Primary

    Memory management · CPC title

  • using a cache memory · CPC title

  • G09G5/393Primary

    Arrangements for updating the contents of the bit-mapped memory · CPC title

  • Filling planar surfaces by adding surface attributes, e.g. adding colours or textures · CPC title

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What does patent US2016148339A1 cover?
An apparatus and method are described for the frame-to-frame coherency algorithm for sort-last architecture. In one embodiment of the invention, if a tile of pixels is covered completely by one triangle from a static draw call in one frame, then that tile is marked with that draw call's identifier. For the next frame, if the same static draw call is drawn, the same tile will be visited, and if …
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification G06T1/60. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu May 26 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).