Detecting and configuring of external io enclosure

Patent metadata

Field	Value
Publication number	US-2016147697-A1
Application number	US-201414549912-A
Country	US
Kind code	A1
Filing date	Nov 21, 2014
Priority date	Nov 21, 2014
Publication date	May 26, 2016
Grant date	—

Abstract

A method, system and computer program product are provided for detecting and configuring an external input/output (IO) enclosure in a computer system. A PCIE Host Bridge (PHB) in a system unit is connected to a plurality of PCIE add-in card slots. One or more cables are connected between the PHB and the external enclosure. System firmware including detecting and configuring functions uses sideband structure for detecting a PCIE cable card and configuring the external input/output (IO) enclosure.

First claim

1 - 11 . (canceled)

12 . A computer system for detecting and configuring an external input/output (IO) enclosure, comprising:
a processor; a PCI host bridge (PHB); said PHB connected to said processor and a plurality of PCIE add-in card slots connected to the PHB; one or more cables connecting between the PHB and the external enclosure; system firmware including detecting and configuring functions; and said processor using said system firmware and sideband structure for detecting a PCIE cable card and configuring the external input/output (IO) enclosure.

13 . The system as recited in claim 12 , includes control code stored on a computer readable medium, wherein said control code comprising said system firmware.

14 . The system as recited in claim 12 , includes said processor using said system firmware and sideband structure for detecting cables being connected to the PCIE cable card and connected to an IO drawer.

15 . The system as recited in claim 14 , includes said processor using said system firmware and sideband structure to identify one or more of a plurality of cables connected to different IO drawers.

16 . The system as recited in claim 14 , includes said processor using said system firmware and sideband structure to report to system management functions and customer user interfaces when cables are incorrectly connected to different IO drawers.

17 . The system as recited in claim 14 , includes said processor using said system firmware and sideband structure to determine each cable is properly connected to convey PCIE lanes from the PHB passing through the cable card and cable to the corresponding PCIE lanes of the PCIE slot.

18 . The system as recited in claim 14 , includes said processor using said system firmware and sideband structure to determine when one or more cables within a plurality of cables comprising a single PCIE link is inoperable or disconnected from the cable card or IO drawer, and to determine when other connected cables are able to form an operable PCIE link.

19 . The system as recited in claim 14 , includes said processor using said system firmware and sideband structure to determine when one or more cables within a plurality of cables comprising a single PCIE link is inoperable or disconnected from the cable card or IO drawer, and to determine when other connected cables are unable to form an operable PCIE link.

20 . The system as recited in claim 14 , includes said processor using said system firmware and sideband structure to report to system management functions and customer user interfaces when cables are inoperable or disconnected from the cable card or IO drawer.

Assignees

• IBM

Inventors

• Arroyo Jesse P
• Bauman Ellen M
• Eide Curtis S
• Engel Christopher J
• Nordstrom Gregory M
• Pross Harald
• Sand Thomas R
• Thompson William A

Classifications

• G06F9/4411

  Configuring for operating with peripheral devices; Loading of device drivers · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F9/44505

  Configuring for program initiating, e.g. using registry, configuration files · CPC title

• G06F13/362 Primary

  with centralised access control · CPC title

• G06F13/4068 Primary

  Electrical coupling · CPC title