Multilevel Cache-Based Data Read/Write Method and Apparatus, and Computer System

Patent metadata

Field	Value
Publication number	US-2016147666-A1
Application number	US-201615010376-A
Country	US
Kind code	A1
Filing date	Jan 29, 2016
Priority date	Jul 31, 2013
Publication date	May 26, 2016
Grant date	—

Abstract

A multilevel cache-based data read/write method and a computer system. The method includes acquiring a query address of a physical memory data block in which data is to be read/written, acquiring a cache location attribute of the physical memory data block, querying whether a cache is hit until one cache is hit or all caches are missed, where the querying is performed according to the query address in descending order of levels of caches storable for the physical memory data block, and the levels of the caches are indicated by the cache location attribute, and if one cache is hit, reading/writing the data in the query address of the physical memory data block in the hit cache; or, if all caches are missed, reading/writing the data in the query address of the physical memory data block in a memory.

First claim

What is claimed is:

1 . A cache-based data read/write method applied in a computer system, wherein the computer system comprises a processor, a memory and a plurality of cache memories organized in a hierarchy, and wherein the cache-based data read/write method comprises:
acquiring a first query address by the processor, wherein the first query address indicates a first physical memory data block in which data is to be read/written; acquiring a first cache location attribute of the first physical memory data block, wherein where the first cache location attribute indicates a level in levels of caches storable for the first physical memory data block; querying whether the level of cache is hit until one level of cache is hit or all levels of caches are missed, wherein the querying is performed according to the first query address in descending order of levels of caches storable for the first physical memory data block, and wherein the highest level of cache is indicated in the first cache location attribute; and reading/writing the data in the first query address of the first physical memory data block in a hit level of cache when one level of cache is hit; and reading/writing the data in the first query address of the first physical memory data block in the memory when all levels of caches are missed.

2 . The method according to claim 1 , wherein the first cache location attribute identifies a highest level in levels of caches storable for the first physical memory data block.

3 . The method according to claim 1 , wherein the first cache location attribute is set in a translation lookaside buffer (TLB) for the first physical memory data block according to an access status of the first physical memory data block, and wherein the method further comprises querying, according to attribute information that corresponding to physical memory data blocks and stored in the TLB, the first cache location attribute corresponding to the first query address, wherein the TLB stores the attribute information of a physical memory data block, and wherein the attribute information comprises a correspondence between a query address of the physical memory data block and a cache location attribute of the physical memory data block.

4 . The method according to claim 1 , wherein the first cache location attribute is set in a system register for the first physical memory data block according to the access status of the first physical memory data block, and wherein the method further comprises:
reading the cache location attribute stored in the system register; and using the cache location attribute as the first cache location attribute of the first physical memory data block, wherein the system register is used to store the cache location attribute.

5 . The method according to claim 1 , wherein reading/writing the data in the first query address of the first physical memory data block in the hit level of cache comprises reading/writing the data in the first query address of the first physical memory data block in the hit level of cache using a direct data path to the hit level of cache.

6 . The method according to claim 1 , wherein reading/writing the data in the first query address of the first physical memory data block in the memory comprises reading/writing the data in the first query address of the first physical memory data block in the memory using a direct data path to the memory.

7 . The method according to claim 1 , wherein during data reading, the method further comprises:
refilling, with to-be-read data, a level of cache whose level is higher than the hit level of cache is among the levels of caches storable, indicated by the first cache location attribute when the hit level of cache is a non-highest level in the levels of caches storable, indicated by the first cache location attribute.

8 . The method according to claim 1 , wherein during data reading, the method further comprises:
skipping refilling another cache with data when the hit level of cache is the highest level in the levels of caches storable, indicated by the first cache location attribute.

9 . The method according to claim 1 , wherein during data reading, the method further comprises:
refilling, with to-be-read data, a storable cache indicated by the first cache location attribute when all levels of caches are missed.

10 . The method according to claim 1 , wherein during data writing, after writing the data in the first physical memory data block in the hit level of cache, the method further comprises initiating a shared data consistency request to another cache whose level is not greater than the level of the hit cache among the levels of caches storable, indicated by the first cache location attribute when the written data is shared data.

11 . A computer system having a plurality of cache memories organized in a hierarchy, comprising:
a processor; and a memory coupled to the processor and the plurality of cache memories organized in the hierarchy, wherein the processor is configured to:
acquire a first query address, wherein the first query address is used to indicate a first physical memory data block in which data is to be read/written;
acquire a first cache location attribute of the first physical memory data block, where the first cache location attribute indicates a level in levels of caches storable for the first physical memory data block;
query whether the level of cache is hit until one level of cache is hit or all levels of caches are missed, wherein the querying is performed according to the first query address in descending order of levels of caches storable for the first physical memory data block, and wherein the highest level of cache is indicated in the first cache location attribute; and
read/write the data in the first query address of the first physical memory data block in a hit level of cache when one level of cache is hit; and
read/write the data in the first query address of the first physical memory data block in the memory when all levels of caches are missed.

12 . The computer system according to claim 11 , wherein the first cache location attribute identifies a highest level in levels of caches storable for the first physical memory data block.

13 . The computer system according to claim 11 , wherein the first cache location attribute is set in a translation lookaside buffer (TLB) for the physical memory data block according to an access status of the first physical memory data block, and wherein the processor is further configured to query, according to attribute information that corresponds to physical memory data blocks and stored in the TLB, the first cache location attribute corresponding to the first query address, wherein the TLB stores the attribute information of a physical memory data block, and wherein the attribute information comprises a correspondence between a query address of the physical memory data block and a cache location attribute of the physical memory data block.

14 . The computer system according to claim 11 , wherein the first cache location attribute is set in a system register for the first physical memory data block according to the access status of the first physical memory data block, and wherein the processor is further configured to:
read the cache location attribute stored in the system register; and use the cache location attribute as the first cache location attribute of the first physical memory data block, wherein the system register is used to store the cache location attribute.

15 . The computer system according to claim 11 , wherein the processor is f

Assignees

• Huawei Tech Co Ltd

Inventors

• Li Ye
• Zhang Lixin
• Hou Rui
• Zhang Ke

Classifications

• G06F3/064

  Management of blocks · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F2212/50

  Control mechanisms for virtual memory, cache or TLB · CPC title

• G06F12/0897 Primary

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title