Providing shared cache memory allocation control in shared cache memory systems

Patent metadata

Field	Value
Publication number	US-2016147656-A1
Application number	US-201514861025-A
Country	US
Kind code	A1
Filing date	Sep 22, 2015
Priority date	Nov 25, 2014
Publication date	May 26, 2016
Grant date	—

Abstract

Providing shared cache memory allocation control in shared cached memory systems is disclosed. In one aspect, a cache controller of a shared cache memory system comprising a plurality of cache lines is provided. The cache controller comprises a cache allocation circuit providing a minimum mapping bitmask for mapping a Quality of Service (QoS) class to a minimum partition of the cache lines, and a maximum mapping bitmask for mapping the QoS class to a maximum partition of the cache lines. The cache allocation circuit receives a memory access request comprising a QoS identifier (QoSID) of the QoS class, and is configured to determine whether the memory access request corresponds to a cache line of the plurality of cache lines. If not, the cache allocation circuit selects, as a target partition, the minimum partition mapped to the QoS class or the maximum partition mapped to the QoS class.

First claim

What is claimed is:

1 . A cache controller of a shared cache memory system comprising a plurality of cache lines, the cache controller comprising a cache allocation circuit comprising:
a minimum mapping bitmask for mapping a Quality of Service (QoS) class of a plurality of QoS classes to a minimum partition of the plurality of cache lines; a maximum mapping bitmask for mapping the QoS class of the plurality of QoS classes to a maximum partition of the plurality of cache lines; and the cache allocation circuit configured to:
receive a memory access request comprising a QoS identifier (QoSID) corresponding to the QoS class of the plurality of QoS classes;
determine whether the memory access request corresponds to a cache line of the plurality of cache lines; and
responsive to determining that the memory access request does not correspond to the cache line of the plurality of cache lines:
select, as a target partition, one of the minimum partition mapped to the QoS class corresponding to the QoSID by the minimum mapping bitmask and the maximum partition mapped to the QoS class corresponding to the QoSID by the maximum mapping bitmask; and
allocate a cache line within the target partition for a cache fill operation.

2 . The cache controller of claim 1 , wherein the cache allocation circuit is configured to allocate the cache line within the target partition by:
identifying one or more cache lines of the plurality of cache lines within the target partition as one or more eviction candidates; and evicting an eviction candidate of the one or more eviction candidates from the shared cache memory system.

3 . The cache controller of claim 1 , wherein:
the cache allocation circuit is further configured to provide an average allocation target value; the cache allocation circuit is configured to select, as the target partition, the one of the minimum partition and the maximum partition to cause an actual allocation of cache lines allocated to the QoS class corresponding to the QoSID to approach the average allocation target value.

4 . The cache controller of claim 3 , wherein:
the cache controller further comprises a cache usage monitor for providing an indication of an allocation of the plurality of cache lines among the plurality of QoS classes; and the cache allocation circuit is configured to select, as the target partition, the one of the minimum partition and the maximum partition based on the indication provided by the cache usage monitor.

5 . The cache controller of claim 1 , wherein the cache allocation circuit is configured to select, as the target partition, the one of the minimum partition and the maximum partition by probabilistically selecting the one of the minimum partition and the maximum partition.

6 . The cache controller of claim 5 , further comprising a probability function provider circuit;
wherein the cache allocation circuit is configured to probabilistically select the one of the minimum partition and the maximum partition based on the probability function provider circuit.

7 . The cache controller of claim 1 , wherein the minimum mapping bitmask and the maximum mapping bitmask map the QoS class of the plurality of QoS classes to a same partition of the plurality of cache lines that is exclusive to the QoS class.

8 . The cache controller of claim 1 , wherein:
the minimum mapping bitmask maps the QoS class of the plurality of QoS classes to the minimum partition that is exclusive to the QoS class; and the maximum mapping bitmask maps the QoS class of the plurality of QoS classes to the maximum partition that is not exclusive to the QoS class.

9 . The cache controller of claim 1 integrated into an integrated circuit (IC).

10 . The cache controller of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a mobile phone; a cellular phone; a computer; a portable computer; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; and a portable digital video player.

11 . A cache controller of a shared cache memory system, comprising:
a means for receiving a memory access request comprising a Quality of Service (QoS) identifier (QoSID) corresponding to a QoS class of a plurality of QoS classes; a means for determining whether the memory access request corresponds to a cache line of a plurality of cache lines of the shared cache memory system; a means for selecting, as a target partition, one of a minimum partition mapped to the QoS class corresponding to the QoSID by a minimum mapping bitmask and a maximum partition mapped to the QoS class corresponding to the QoSID by a maximum mapping bitmask, responsive to determining that the memory access request does not correspond to the cache line of the plurality of cache lines; and a means for allocating the cache line of the plurality of cache lines within the target partition for a cache fill operation, responsive to determining that the memory access request does not correspond to the cache line of the plurality of cache lines.

12 . The cache controller of claim 11 , wherein the means for allocating the cache line within the target partition comprises:
a means for identifying one or more cache lines of the plurality of cache lines within the target partition as one or more eviction candidates; and a means for evicting an eviction candidate of the one or more eviction candidates from the shared cache memory system.

13 . The cache controller of claim 11 , further comprising a means for providing an average allocation target value;
wherein the means for selecting, as the target partition, the one of the minimum partition and the maximum partition comprises a means for selecting the one of the minimum partition and the maximum partition to cause an actual allocation of cache lines allocated to the QoS class corresponding to the QoSID to approach the average allocation target value.

14 . The cache controller of claim 13 , wherein the means for selecting, as the target partition, the one of the minimum partition and the maximum partition comprises a means for selecting the one of the minimum partition and the maximum partition based on an indication of an allocation of the plurality of cache lines among the plurality of QoS classes provided by a cache usage monitor.

15 . The cache controller of claim 11 , wherein the means for selecting, as the target partition, the one of the minimum partition and the maximum partition comprises a means for probabilistically selecting the one of the minimum partition and the maximum partition.

16 . The cache controller of claim 15 , wherein the means for probabilistically selecting the one of the minimum partition and the maximum partition is based on a probability function provider circuit.

17 . The cache controller of claim 11 , wherein the minimum mapping bitmask and the maximum mapping bitmask map the QoS class of the plurality of QoS classes to a same partition of the plurality of cache lines that is exclusive to the QoS class.

18 . The cache controller of claim 11 , wherein:
the minimum mapping bitmask maps the QoS class of the plurality of QoS classes to the minimum partition that is exclusive to the QoS class; and the maximum ma

Assignees

• Qualcomm Inc

Inventors

• Hower Derek Robert
• Cain Iii Harold Wade

Classifications

• G06F12/0842

  for multiprocessing or multitasking · CPC title

• G06F2212/62

  Details of cache specific to multiprocessor cache arrangements · CPC title

• G06F12/0846

  Cache with multiple tag or data arrays being simultaneously accessible · CPC title

• G06F12/128

  adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel · CPC title

• G06F12/084 Primary

  with a shared cache · CPC title