Single wire system clock signal generation

Patent metadata

Field	Value
Publication number	US-2016142201-A1
Application number	US-201414546564-A
Country	US
Kind code	A1
Filing date	Nov 18, 2014
Priority date	Nov 18, 2014
Publication date	May 19, 2016
Grant date	—

Abstract

This specification describes an integrated circuit comprising: a single wire interface; a clock circuit configured to detect a voltage from the single wire interface and to generate a clock signal having a frequency that is based on the detected voltage; and a digital system coupled with the single wire interface and the clock circuit. The digital system is configured to: receive a data signal from the single wire interface; power the digital system using a power signal from the single wire interface; and perform one or more operations clocked by the clock signal.

First claim

What is claimed is:

1 . An integrated circuit comprising:
a single wire interface; a clock circuit configured to detect a voltage from the single wire interface and to generate a clock signal having a frequency that is based on the detected voltage; and a digital system coupled with the single wire interface and the clock circuit, the digital system configured to:
receive a data signal from the single wire interface;
power the digital system using a power signal received from the single wire interface; and
perform one or more operations clocked by the clock signal.

2 . The integrated circuit of claim 1 , wherein the clock circuit is configured to decrease the frequency of the clock signal in response to determining that the detected voltage is below a threshold voltage, thereby decreasing an operational speed of the digital system.

3 . The integrated circuit of claim 1 , wherein the clock circuit is configured to adjust the frequency of the clock signal to a target frequency within a range of specified frequencies based on a difference between the detected voltage and a threshold voltage.

4 . The integrated circuit of claim 1 , wherein the clock circuit is configured to detect a rectified voltage from the single wire interface over a period of time and adjust the frequency of the clock signal based on the detected rectified voltage.

5 . The integrated circuit of claim 1 , wherein the clock circuit comprises a digital circuit comprising a plurality of frequency dividers.

6 . The integrated circuit of claim 1 , wherein the clock circuit comprises an analog circuit.

7 . The integrated circuit of claim 1 , wherein the clock circuit is configured to cease generating the clock signal if the voltage from the single wire interface drops to zero for a period of time.

8 . The integrated circuit of claim 1 , wherein the digital system is configured to perform one or more cryptographic operations.

9 . A method comprising:
receiving a data signal from a single wire interface of a digital system; powering the digital system using a power signal received from the single wire interface; detecting a voltage from the single wire interface; generating, by a clock circuit, a clock signal having a frequency based on the detected voltage; and performing, at the digital system, one or more operations clocked by the clock signal having the frequency based on the detected voltage.

10 . The method of claim 9 , comprising decreasing the frequency of the clock signal in response to determining that the detected voltage is below a threshold voltage, thereby decreasing an operational speed of the digital system.

11 . The method of claim 9 , comprising adjusting the frequency of the clock signal to a target frequency within a range of specified frequencies based on a difference between the detected voltage and a threshold voltage.

12 . The method of claim 9 , comprising detecting a rectified voltage from the single wire interface over a period of time and adjusting the frequency of the clock signal based on the detected rectified voltage.

13 . The method of claim 9 , comprising generating the clock signal using a digital circuit comprising a plurality of frequency dividers.

14 . The method of claim 9 , comprising generating the clock signal using an analog circuit.

15 . The method of claim 9 , comprising ceasing generating the clock signal if the voltage from the single wire interface drops to zero for a period of time.

16 . The method of claim 9 , comprising performing one or more cryptographic operations using the generated clock signal.

17 . A system comprising:
a user system; and a single wire system coupled with the user system by a single wire interface, the single wire system comprising:
a single wire interface;
a clock circuit configured to detect a voltage from the single wire interface and to generate a clock signal having a frequency based on the detected voltage; and
a digital system coupled with the single wire interface and the clock circuit, the digital system configured to receive a data signal from the user system from the single wire interface, to power the digital system using a power signal from the user system from the single wire interface, and to perform one or more operations clocked by the clock signal.

18 . The system of claim 17 , wherein the clock circuit is configured to decrease the frequency of the clock signal in response to determining that the detected voltage is below a threshold voltage, thereby decreasing an operational speed of the digital system.

19 . The system of claim 17 , wherein the clock circuit is configured to adjust the frequency of the clock signal to a target frequency within a range of specified frequencies based on a difference between the detected voltage and a threshold voltage.

20 . The system of claim 17 , wherein the clock circuit is configured to detect a rectified voltage from the single wire interface over a period of time and adjust the frequency of the clock signal based on the detected rectified voltage.

21 . The integrated circuit of claim 1 , wherein the frequency is proportional to the detected voltage.

22 . The integrated circuit of claim 1 , wherein the frequency is between first and second other frequencies.

23 . The method of claim 9 , wherein the frequency is proportional to the detected voltage.

24 . The method of claim 9 , wherein the frequency is between first and second other frequencies.

25 . The system of claim 1 , wherein the frequency is proportional to the detected voltage.

26 . The system of claim 1 , wherein the frequency is between first and second other frequencies.

Assignees

• Atmel Corp

Inventors

• Weiner Albert S

Classifications

• G06F13/4286 Primary

  using a handshaking protocol, e.g. RS232C link · CPC title

• H04L7/04 Primary

  Speed or phase control by synchronisation signals {(H04L7/0075 takes precedence)} · CPC title

• H04L7/0016

  correction of synchronization errors · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title