Semiconductor device

Patent metadata

Field	Value
Publication number	US-2016141401-A1
Application number	US-201514942528-A
Country	US
Kind code	A1
Filing date	Nov 16, 2015
Priority date	Nov 17, 2014
Publication date	May 19, 2016
Grant date	—

Abstract

A semiconductor device has emitter regions disposed in at least one cell region in a first inter-trench region, not disposed in a middle inter-trench region, and disposed in at least one cell region in the second inter-trench region. Each of the emitter regions is disposed at a position that is not in contact with first trenches but is in contact with two second trenches defining the corresponding cell region.

First claim

1 . A semiconductor device including a semiconductor substrate in which a semiconductor element is disposed, the semiconductor device comprising:
a p-type body region disposed at one portion of the semiconductor substrate in a cross sectional view of the semiconductor substrate; an n-type drift region disposed below the p-type body region in the cross sectional view; a plurality of n-type emitter regions separated from the n-type drift region by the p-type body region and exposed on an upper surface of the semiconductor substrate; a trench extending from the upper surface of the semiconductor substrate, piercing the p-type body region and reaching the n-type drift region in the cross sectional view, wherein the trench comprises, in a plan view of the semiconductor substrate, a plurality of first trenches extending in a first direction and arranged at intervals in a second direction intersecting the first direction, and a plurality of second trenches extending in the second direction and arranged at intervals in the first direction; a gate insulation film disposed on an inner surface of the trench; a gate electrode disposed in the trench; a plurality of inter-trench regions, each of the plurality of inter-trench regions being a region between two adjacent first trenches; and a plurality of cell regions, each of the plurality of cell regions being a region defined by two adjacent first trenches and two adjacent second trenches, wherein the plurality of inter-trench regions comprises:
a first inter-trench region;
a second inter-trench region separated from the first inter-trench region by at least one of the inter-trench regions being interposed in between in the second direction; and
a middle inter-trench region interposed in between the first inter-trench region and the second inter-trench region,
the emitter regions are disposed in at least one cell region in the first inter-trench region, are not disposed in the middle inter-trench region, and are disposed in at least one cell region in the second inter-trench region, and
each of the emitter regions is disposed at a position that is not in contact with the first trenches but is in contact with the two second trenches defining the corresponding cell region.

2 . The semiconductor device according to claim 1 , wherein
the emitter regions are formed in a pair in each of the cell regions, one emitter region of each pair of the emitter regions is in contact with one of the two second trenches defining the corresponding cell region, and the other emitter region of each pair of the emitter regions is in contact with the other of the two second trenches defining the corresponding cell region.

3 . The semiconductor device according to claim 1 , wherein
the plurality of inter-trench regions comprises a plurality of the middle inter-trench regions, and at least one of the second trenches is disposed in at least one of the middle inter-trench regions.

4 . The semiconductor device according to claim 1 , wherein
the emitter regions are in contact with both sides of each of the second trenches in the first direction in the first inter-trench region and the second inter-trench region.

Assignees

• Toyota Motor Co Ltd

Inventors

• Hirabayashi Yasuhiro
• Senoo Masaru

Classifications

• H10D64/117

  Recessed field plates, e.g. trench field plates or buried field plates · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/127

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title

• H10D62/106

  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions · CPC title

• H10D12/481 Primary

  having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs · CPC title