Display device

Patent metadata

Field	Value
Publication number	US-2016141308-A1
Application number	US-201615000096-A
Country	US
Kind code	A1
Filing date	Jan 19, 2016
Priority date	Sep 29, 2006
Publication date	May 19, 2016
Grant date	—

Abstract

By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.

First claim

1 . (canceled)

2 . A semiconductor device comprising:
a first flip-flop; and a second flip-flop, wherein the first flip-flop comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor, wherein the second flip-flop comprises a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a second capacitor, wherein a ratio of a channel width to a channel length of the first transistor is greater than a ratio of a channel width to a channel length of the third transistor, wherein the ratio of the channel width to the channel length of the first transistor is greater than a ratio of a channel width to a channel length of the fifth transistor, wherein the ratio of the channel width to the channel length of the first transistor is greater than a ratio of a channel width to a channel length of the sixth transistor, wherein a ratio of a channel width to a channel length of the seventh transistor is greater than a ratio of a channel width to a channel length of the ninth transistor, wherein the ratio of the channel width to the channel length of the seventh transistor is greater than a ratio of a channel width to a channel length of the eleventh transistor, wherein the ratio of the channel width to the channel length of the seventh transistor is greater than a ratio of a channel width to a channel length of the twelfth transistor, wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor, wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor, wherein one of a source and a drain of the fifth transistor is directly connected to one of a source and a drain of the sixth transistor, wherein a gate of the first transistor is electrically connected to the one of the source and the drain of the fifth transistor, wherein a gate of the second transistor is directly connected to the one of the source and the drain of the fourth transistor, wherein the gate of the second transistor is directly connected to a gate of the sixth transistor, wherein a gate of the fourth transistor is directly connected to a gate of the fifth transistor, wherein the gate of the fourth transistor is directly connected to the other of the source and the drain of the fifth transistor, wherein a first electrode of the first capacitor is directly connected to the gate of the first transistor, wherein a second electrode of the first capacitor is directly connected to the one of the source and the drain of the first transistor, wherein one of a source and a drain of the seventh transistor is directly connected to one of a source and a drain of the eighth transistor, wherein one of a source and a drain of the ninth transistor is electrically connected to one of a source and a drain of the tenth transistor, wherein one of a source and a drain of the eleventh transistor is directly connected to one of a source and a drain of the twelfth transistor, wherein a gate of the seventh transistor is electrically connected to the one of the source and the drain of the eleventh transistor, wherein a gate of the eighth transistor is directly connected to the one of the source and the drain of the tenth transistor, wherein the gate of the eighth transistor is directly connected to a gate of the twelfth transistor, wherein a gate of the tenth transistor is directly connected to a gate of the eleventh transistor, wherein the gate of the tenth transistor is directly connected to the other of the source and the drain of the eleventh transistor, wherein a first electrode of the second capacitor is directly connected to the gate of the seventh transistor, wherein a second electrode of the second capacitor is directly connected to the one of the source and the drain of the seventh transistor, wherein the other of the source and the drain of the first transistor is directly connected to a first wiring, wherein the other of the source and the drain of the third transistor is directly connected to a second wiring, wherein the other of the source and the drain of the seventh transistor is directly connected to the second wiring, wherein the other of the source and the drain of the ninth transistor is directly connected to the first wiring, and wherein the one of the source and the drain of the first transistor is directly connected to the gate of the eleventh transistor.

3 . The semiconductor device according to claim 2 ,
wherein a same voltage is supplied to the other of the source and the drain of the second transistor, the other of the source and the drain of the fourth transistor, the other of the source and the drain of the sixth transistor, the other of the source and the drain of the eighth transistor, the other of the source and the drain of the tenth transistor, and the other of the source and the drain of the twelfth transistor.

4 . The semiconductor device according to claim 2 ,
wherein a first clock signal is input to the first wiring, and wherein a second clock signal is input to the second wiring.

5 . The semiconductor device according to claim 2 ,
wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor comprise a polycrystalline semiconductor.

6 . A display device comprising:
a pixel portion; a scan line driver circuit; and a signal line driver circuit, wherein the pixel portion and the scan line driver circuit are formed over a substrate, wherein the scan line driver circuit comprises a first flip-flop and a second flip-flop, wherein the first flip-flop comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor, wherein the second flip-flop comprises a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a second capacitor, wherein a ratio of a channel width to a channel length of the first transistor is greater than a ratio of a channel width to a channel length of the third transistor, wherein the ratio of the channel width to the channel length of the first transistor is greater than a ratio of a channel width to a channel length of the fifth transistor, wherein the ratio of the channel width to the channel length of the first transistor is greater than a ratio of a channel width to a channel length of the sixth transistor, wherein a ratio of a channel width to a channel length of the seventh transistor is greater than a ratio of a channel width to a channel length of the ninth transistor, wherein the ratio of the channel width to the channel length of the seventh transistor is greater than a ratio of a channel width to a channel length of the eleventh transistor, wherein the ratio of the channel width to the channel length of the seventh transistor is greater than a ratio of a channel width to a channel length of the twelfth transistor, wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor, wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor, wherein one of a source and a drain of the fifth transistor is directly connected to one of a source and a drain of the sixth transistor, wherein

Assignees

• Semiconductor Energy Lab

Inventors

• Umezaki Atsushi

Classifications

• H01H71/02

  Housings; Casings; Bases; Mountings · CPC title

• H01H71/10

  Operating or release mechanisms · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G02F1/133345

  Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence) · CPC title

• G09G2320/043

  Preventing or counteracting the effects of ageing · CPC title