Bumpless build-up layer package including a release layer

Patent metadata

Field	Value
Publication number	US-2016141265-A1
Application number	US-201615007454-A
Country	US
Kind code	A1
Filing date	Jan 27, 2016
Priority date	Dec 21, 2012
Publication date	May 19, 2016
Grant date	—

Abstract

An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a release layer having a lower release layer surface, an upper release layer surface parallel to the lower release layer surface, and at least one release layer side, the release layer coupled with the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the release layer side and lower release layer surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface.

First claim

1 . (canceled)

2 . A method of building up a microelectronic die package, the method comprising:
coupling an resin layer onto a metal film; coupling a release layer onto the resin layer; adhering the release layer to a substrate with a weak adhesion bond; creating a cavity in the metal film; and coupling a microelectronic die onto the metal film, inside the cavity.

3 . The method of claim 2 , wherein coupling the resin layer onto the metal film includes spraying the resin layer onto the metal film.

4 . The method of claim 3 , wherein coupling the resin layer onto the metal film includes spraying the resin layer onto the metal film in a pattern that covers less than an entire surface of the metal film.

5 . The method of claim 4 , comprising coupling the release layer onto the resin layer in a pattern that covers an entire exposed surface of the resin layer.

6 . The method of claim 2 , wherein coupling the resin layer onto the metal film includes rolling the resin layer from a roll of resin layer onto the metal film.

7 . The method of claim 6 , wherein coupling the resin layer onto the metal film includes rolling the resin layer onto the metal film in a pattern that covers less than an entire surface of the metal film, including periodically cutting the roll.

8 . The method of claim 2 , comprising coupling a primer on the resin layer, wherein coupling the release layer onto the resin layer includes coupling the release layer onto the primer.

9 . The method of claim 2 , comprising creating the cavity includes etching the metal film.

10 . The method of claim 2 , comprising forming build-up layers on the metal film, around the top microelectronic die.

11 . The method of claim 2 , further comprising adhering the release layer to a surface of a substrate with a weak adhesion bond including pressing the release layer to the surface of the substrate under a pressure at a temperature in excess of an ambient temperature.

12 . A method of packaging a microelectronic die, comprising:
coupling a top resin layer onto a top metal film; coupling a top release layer onto the top resin layer; coupling a bottom resin layer onto a bottom metal film; coupling a bottom release layer onto the bottom resin layer; adhering the top release layer to a top surface of a substrate with a weak adhesion bond; adhering the bottom release layer to a bottom surface of the substrate with a weak adhesion bond; creating a top cavity in the top metal film; creating a bottom cavity in the bottom metal film; coupling a top microelectronic die to the top metal film in the top cavity; coupling a bottom microelectronic die to the bottom metal film in the bottom cavity; cutting the top metal film, top release layer, top resin, bottom metal film, bottom release layer, bottom resin and substrate, with a cut line disposed between a portion of the top resin layer that is coupled with the substrate and between a portion of the bottom resin layer that is coupled with the substrate; overcoming the weak adhesion bond separating the top release layer from the top surface of the substrate; and overcoming the weak adhesion bond separating the bottom release layer from the bottom surface of the substrate.

13 . The method of claim 12 , comprising creating the top cavity includes etching the top metal film, and creating the bottom cavity includes etching the bottom metal film.

14 . The method of claim 12 , comprising forming top build-up layers on the top metal film, around the top microelectronic die onto the top metal film, and forming bottom build-up layers on the bottom metal film, around the bottom microelectronic die onto the bottom metal film.

15 . The method of claim 12 , wherein adhering the top release layer to a top surface of a substrate with a weak adhesion bond includes pressing the top release layer to the top surface of the substrate under a pressure at a temperature in excess of an ambient temperature, and wherein adhering the bottom release layer to a bottom surface of a substrate with a weak adhesion bond includes concurrently pressing the bottom release layer to the bottom surface of the substrate under the same pressure and temperature.

16 . The method of claim 12 , wherein coupling the top resin layer onto the top metal film includes spraying the top resin layer onto the top metal film.

17 . The method of claim 16 , wherein coupling the top resin layer onto the top metal film includes spraying the resin layer onto the metal film in a pattern that covers less than an entire surface of the metal film.

18 . The method of claim 17 , comprising coupling the top release layer onto the top resin layer in a pattern that covers an entire exposed surface of the top resin layer.

19 . The method of claim 12 , wherein coupling the top resin layer onto the top metal film includes rolling the top resin layer from a roll of resin onto the top metal film.

20 . The method of claim 19 , wherein coupling the top resin layer onto the top metal film includes rolling the top resin layer onto the top metal film in a pattern that covers less than an entire surface of the top metal film and including periodically cutting the roll.

21 . The method of claim 12 , comprising coupling a primer on the top resin layer, wherein coupling the top release layer onto the top resin layer includes coupling the top release layer onto the primer.

Assignees

• Intel Corp

Inventors

• Jin Liwen
• Seneviratne Dilan

Classifications

• H10W72/874

  On different surfaces · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title

• H10P72/7424

  used as a support during the manufacture of self-supporting substrates · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title