Memory device

Patent metadata

Field	Value
Publication number	US-2016141023-A1
Application number	US-201514942263-A
Country	US
Kind code	A1
Filing date	Nov 16, 2015
Priority date	Nov 17, 2014
Publication date	May 19, 2016
Grant date	—

Abstract

Disclosed is a memory device. The memory device includes a bit-cell comprising a cross-coupled inverter and pass gate transistor connected to data storage node of the cross-coupled inverter, a read buffer transistor having a drain terminal connected to a bit line for read operation and a gate terminal connected to the pass gate transistor, a write operation transistor connected between the pass gate transistor and a bit line for write operation, and a drive transistor unit which is connected to a local line between the pass gate transistors and the write operation transistor and which provide a voltage to a gate terminal of the read buffer transistor based on a data value stored at the bit-cell.

First claim

What is claimed is:

1 . A memory device, comprising:
a bit-cell comprising a cross-coupled inverter and pass gate transistor connected to data storage node of the cross-coupled inverter; a read buffer transistor having a drain terminal connected to a bit line for read operation and a gate terminal connected to the pass gate transistor; a write operation transistor connected between the pass gate transistor and a bit line for write operation; and a drive transistor unit connected to a local line between the pass gate transistor and the write operation transistor, the drive transistor unit providing a voltage to a gate terminal of the read buffer transistor based on a data value stored at the bit-cell.

2 . The memory device of claim 1 , wherein the drive transistor unit comprises:
a first drive transistor having a drain terminal connected to a first local line between a first pass gate transistor and a first write operation transistor, and a gate terminal connected to a second local line between a second pass gate transistor and a second write operation transistor, the first pass gate transistor being placed near a first data storage node of two data storage nodes, the second pass gate transistor being placed near a second data storage node of the two data storage nodes; a second drive transistor having a gate terminal connected to the first local line and a drain terminal connected to the second local line; and a supply voltage application unit configured to apply a driving voltage corresponding to a supply voltage to source terminals of the first drive transistor and the second drive transistor during a read operation.

3 . The memory device of claim 2 , wherein the drive transistor unit drives the voltage of the gate terminal of the read buffer transistor by applying a voltage corresponding to the driving voltage to a local line, corresponding to a data storage node storing a logic 1, during a read operation.

4 . The memory device of claim 2 , wherein the supply voltage application unit comprises:
a third drive transistor having a drain terminal connected to source terminals of the first drive transistor and the second drive transistor and a source terminal to which the supply voltage is applied.

5 . The memory device of claim 4 , wherein voltage of a word line for read operation is applied to a gate terminal of the third drive transistor and a source terminal of the read buffer transistor.

6 . The memory device of claim 5 , further comprising:
a block mask transistor connected between the local line and the bit line for write operation, the block mask transistor connecting the bit line for write operation with the local line during a hold operation.

7 . The memory device of claim 6 , wherein during a read operation, after voltage of a gate terminal of the block mask transistor is reduced, a voltage of a word line of the bit cell where the read operation is performed increases, and the voltage of the word line for read operation decreases.

8 . The memory device of claim 1 , wherein during a read operation, a suppression voltage lower than a supply voltage is applied to a word line corresponding to the bit-cell in which the read operation is performed.

9 . A memory device, comprising:
a plurality of bit-cells each comprising a cross-coupled inverter, a first pass gate transistor connected to a first data storage node of the cross-coupled inverter, and a second pass gate transistor connected to a second data storage node of the cross-coupled inverter, wherein first pass gate transistors of the bit-cells belonging to a predetermined group are connected to a first local line, and second pass gate transistors of the bit-cells are connected to a second local line, and wherein the memory device further comprises: a first write operation transistor connected between the first local line and a first bit line for write operation, a second write operation transistor connected between the second local line and a second bit line for write operation, a first read buffer transistor having a drain terminal connected to a first bit line for read operation and a gate terminal connected to the first local line, a second read buffer transistor having a drain terminal connected to a second bit line for read operation and a gate terminal connected to the second local line, and a drive transistor unit comprising a first drive transistor having a drain terminal connected to the first local line and a gate terminal connected to the second local line and a second drive transistor having a drain terminal connected to the second local line and a gate terminal connected to the first local line.

10 . The memory device of claim 9 , wherein the drive transistor unit further comprises:
a supply voltage application unit applying a driving voltage corresponding to a supply voltage to source terminals of the first drive transistor and the second drive transistor during a read operation.

11 . The memory device of claim 10 , wherein the drive transistor unit applies a voltage corresponding to the driving voltage to a local line, corresponding to a data storage node storing a logic 1, during a read operation to drive a voltage of the gate terminal of one of the first read buffer transistor and the second read buffer transistor.

12 . The memory device of claim 10 , wherein the supply voltage application unit comprises:
a third drive transistor having a drain terminal connected to source terminals of the first drive transistor and the second drive transistor and a source terminal to which the supply voltage is applied.

13 . The memory device of claim 9 , further comprising:
a first block mask transistor connected between the first local line and the first bit line for write operation, the first block mask transistor connecting the first bit line for write operation with the first local line during a hold operation; and a second block mask transistor connected between the second local line and the second bit line for write operation, the second block mask transistor connecting the second bit line for write operation with the second local line during a hold operation.

14 . The memory device of claim 9 , wherein during a read operation, a suppression voltage lower than a supply voltage is applied to a word line corresponding to a bit-cell in which a read operation is performed.

15 . The memory device of claim 9 , wherein a negative voltage lower than a ground voltage is applied to one of the first bit line for write operation and the second bit line for write operation during a write operation, and
wherein a suppression voltage lower than a supply voltage is applied to a word line corresponding to a bit-cell in which a write operation is performed.

16 . A memory device, comprising:
a plurality of bit-cells each comprising a cross-coupled inverter, a first pass gate transistor connected to a first data storage node of the cross-coupled inverter, and a second pass gate transistor connected to a second data storage node of the cross-coupled inverter, wherein first pass gate transistors of the bit-cells belonging to a predetermined group are connected to a first local line, and second pass gate transistors of the bit-cells are connected to a second local line, and wherein the memory device further comprises: a drive transistor unit connected between the first local line and the second local line, the drive transistor unit applying a voltage corresponding to the driving voltage to a local line, corresponding to a data storage node storing a logic 1, during a read operation.

Assignees

• Univ Yonsei Iacf

Inventors

• Jung Seongook
• Kang Kyoman
• Jeong Hanwool
• Yang Young Hwi
• Park Juhyun

Classifications

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title

• G11C11/4125 Primary

  Cells incorporating circuit means for protecting against loss of information · CPC title