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Memory device including power-up control circuit, and memory system having the same
US2016141015A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016141015-A1 |
| Application number | US-201514837294-A |
| Country | US |
| Kind code | A1 |
| Filing date | Aug 27, 2015 |
| Priority date | Nov 14, 2014 |
| Publication date | May 19, 2016 |
| Grant date | — |
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Abstract
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A memory device may include a power-up control circuit and a first set of boost voltage generators. The power-up control circuit may be configured to consecutively activate a first set of power-up signals with a first delay time between each power-up signal of the first set of power-up signals in response to a rise of a power supply voltage and a reset signal having a first logic level at an initial stage of power-up. The first set of boost voltage generators may be configured to generate an internal boost voltage based on an external boost voltage and the first set of power-up signals. The first set of boost voltage generators may be configured to activate before the reset signal transitions from the first logic level to a second logic level opposite to the first logic level.
First claim
Opening claim text (preview).
What is claimed is: 1 . A memory device comprising: a power-up control circuit configured to consecutively activate a first set of power-up signals with a first delay time between each power-up signal of the first set of power-up signals in response to a rise of a power supply voltage and a reset signal having a first logic level at an initial stage of power-up; and a first set of boost voltage generators configured to generate an internal boost voltage based on an external bo…
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- G11C11/4074Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US2016141015A1 cover?
- A memory device may include a power-up control circuit and a first set of boost voltage generators. The power-up control circuit may be configured to consecutively activate a first set of power-up signals with a first delay time between each power-up signal of the first set of power-up signals in response to a rise of a power supply voltage and a reset signal having a first logic level at an in…
- Who is the assignee on this patent?
- Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification G11C11/4074. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Thu May 19 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).