Recovery improvement for quiesced systems

Patent metadata

Field	Value
Publication number	US-2016140002-A1
Application number	US-201414571512-A
Country	US
Kind code	A1
Filing date	Dec 16, 2014
Priority date	Nov 17, 2014
Publication date	May 19, 2016
Grant date	—

Abstract

Methods and apparatuses for performing a quiesce operation during a processor recovery action is provided. A processor performs a processor recovery action. A processor retrieves a quiesce status of a computer system from a shared cache with a second processor. A processor determines a quiesce status of the first processor based, a least in part, on the retrieved quiesce status of the computer system.

First claim

What is claimed is:

1 . A method for performing a quiesce operation during a processor recovery action, the method comprising:
performing, by a first processor, a processor recovery action; retrieving, by the first processor, a quiesce status of a computer system from a shared cache with a second processor; and determining, by the first processor, a quiesce status of the first processor based, at least in part, on the retrieved quiesce status of the computer system.

2 . The method of claim 1 , wherein the shared cache is a L3 cache of the computer system.

3 . The method of claim 2 , wherein the quiesce status of the computer system is protected with an error-correcting code.

4 . The method of claim 1 , the method further comprising:
receiving, by the computer system, a quiesce request from a second processor, wherein the quiesce request is for one or more instruction requiring the computer system to be quiesced; updating, by the computer system, the quiesce status of the computer system in response to the received quiesce request from the second processor; and sending, by the computer system, the quiesce status of the computer system to at least the first processor.

5 . The method of claim 4 , the method further comprising:
receiving, by the first processor, the quiesce status of the computer system; determining, by the first processor, a response to the quiesce request of the second processor; and sending, by the first processor, the response to the computer system.

6 . The method of claim 5 , the method further comprising:
updating, by the computer system, the quiesce status of the computer system based on the response of the first processor, wherein the response of the first processor includes a quiesce request from the first processor.

7 . The method of claim 6 , the method further comprising:
determining, by the computer system, a priority of the quiesce requests of the first processor and second processor; and sending, by the computer system, the determined priority to the first processor and the second processor.

Assignees

• IBM

Inventors

• Fee Michael
• Gaertner Ute
• Heller Lisa C
• Lehnert Frank
• Navarro Jennifer A
• Wisniewski Rebecca S

Classifications

• G06F11/1064 Primary

  in cache or content addressable memories · CPC title

• G06F11/2041 Primary

  with more than one idle spare processing component · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F2212/314

  In storage network, e.g. network attached cache · CPC title

• G06F12/084

  with a shared cache · CPC title