Morton coordinate adjustment processors, methods, systems, and instructions

Patent metadata

Field	Value
Publication number	US-2016139931-A1
Application number	US-201414542004-A
Country	US
Kind code	A1
Filing date	Nov 14, 2014
Priority date	Nov 14, 2014
Publication date	May 19, 2016
Grant date	—

Abstract

A processor includes a decode unit to decode an instruction that is to indicate a source packed data operand to include Morton coordinates, a dimensionality of a multi-dimensional space having points that the Morton coordinates are to be mapped to, a given dimension of the multi-dimensional space, and a destination. The execution unit is coupled with the decode unit. The execution unit, in response to the decode unit decoding the instruction, stores a result packed data operand in the destination. The result operand is to include Morton coordinates that are each to correspond to a different one of the Morton coordinates of the source operand. The Morton coordinates of the result operand are to be mapped to points in the multi-dimensional space that differ from the points that the corresponding Morton coordinates of the source operand are to be mapped to by a fixed change in the given dimension.

First claim

1 . A processor comprising:
a plurality of packed data registers; a decode unit to decode an instruction, wherein the instruction is to indicate a source packed data operand that is to include a plurality of Morton coordinates, a dimensionality of a multi-dimensional space having points that the Morton coordinates are to be mapped to, a given dimension of the multi-dimensional space, and a destination storage location; and an execution unit coupled with the packed data registers and the decode unit, the execution unit, in response to the decode unit decoding the instruction, to store a result packed data operand in the destination storage location, wherein the result packed data operand is to include a plurality of Morton coordinates that are each to correspond to a different one of the Morton coordinates of the source packed data operand, wherein the Morton coordinates of the result packed data operand are to be mapped to points in the multi-dimensional space that differ from the points that the corresponding Morton coordinates of the source packed data operand are to be mapped to by a fixed change in the given dimension indicated by the instruction.

2 . The processor of claim 1 , wherein the execution unit is to store the result packed data operand in which the fixed change in the given dimension is a unit decrement in the given dimension.

3 . The processor of claim 1 , wherein the execution unit is to generate each Morton coordinate of the result packed data operand by:
setting all lowest order zeroed bits corresponding to the given dimension of each corresponding Morton coordinate of the source packed data operand, which are lower order than each lowest order set bit corresponding to the given dimension of each Morton coordinate of the source packed data operand; and clearing the lowest order set bit corresponding to the given dimension of each Morton coordinate of the source packed data operand.

4 . The processor of claim 1 , wherein the decode unit is to decode the instruction which is to indicate the dimensionality of the multi-dimensional space as being any one of at least two dimensional and three dimensional.

5 . The processor of claim 4 , wherein the decode unit is to decode the instruction which is to indicate the dimensionality of the multi-dimensional space as being any one of said two dimensional, said three dimensional, and four dimensional.

6 . The processor of claim 1 , wherein the decode unit is to decode the instruction which is to have an immediate to indicate the dimensionality of the multi-dimensional space.

7 . The processor of claim 1 , wherein the decode unit is to decode the instruction which is to have an opcode that is to indicate the dimensionality of the multi-dimensional space.

8 . The processor of claim 1 , wherein the decode unit is to decode the instruction which is to have an immediate that is to include at least two bits to indicate the given dimension as being any one of at least two different dimensions.

9 . The processor of claim 1 , wherein the decode unit is to decode the instruction which is to have at least two bits to indicate the given dimension as being any one of at least three different dimensions.

10 . The processor of claim 1 , wherein the execution unit is to generate the Morton coordinates of the result packed data operand without de-interleaving bits of the Morton coordinates of the source packed data operand that correspond to different dimensions.

11 . The processor of claim 1 , wherein the execution unit is to store the result packed data operand having at least one Morton coordinate that is not to be in sequential Morton order with a corresponding Morton coordinate of the source packed data operand.

12 . The processor of claim 1 , further comprising:
a branch prediction unit to predict branches; an instruction prefetch unit coupled with the branch prediction unit, the instruction prefetch unit to prefetch instructions including the instruction; a level 1 (L1) instruction cache coupled with the instruction prefetch unit, the L1 instruction cache to store instructions including the instruction; an L1 data cache to store data; a level 2 (L2) cache coupled with the L1 instruction cache and the L1 data cache, the L2 cache to to store data and instructions; an instruction fetch unit coupled with the L1 instruction cache and the decode unit to fetch the instruction from the L1 instruction cache and provide the instruction to the decode unit; and a register rename unit coupled with the packed data registers to rename the packed data registers.

13 . A method in a processor comprising:
receiving a instruction, the instruction indicating a source packed data operand that includes a plurality of Morton coordinates, a dimensionality of a multi-dimensional space having points that the Morton coordinates are mapped to, a given dimension of the multi-dimensional space, and a destination storage location; and storing a result packed data operand in the destination storage location responsive to performing the instruction, the result packed data operand including a plurality of Morton coordinates that each correspond to a different one of the Morton coordinates of the source packed data operand, wherein the Morton coordinates of the result packed data operand are mapped to points in the multi-dimensional space that differ from the points that the corresponding Morton coordinates of the source packed data operand are mapped to by a fixed change in the given dimension indicated by the instruction.

14 . The method of claim 13 , wherein storing the result packed data operand comprises storing the result packed data operand in which the fixed change is a unit decrement in the given dimension.

15 . The method of claim 13 , further comprising generating each Morton coordinate of the result packed data operand by:
setting all lowest order zeroed bits corresponding to the given dimension of each corresponding Morton coordinate of the source packed data operand, which are lower order than each lowest order set bit corresponding to the given dimension of each Morton coordinate of the source packed data operand; and clearing the lowest order set bit corresponding to the given dimension of each Morton coordinate of the source packed data operand.

16 . The method of claim 13 , wherein receiving comprises receiving the instruction that is able to indicate the dimensionality of the multi-dimensional space as being any one of at least two dimensional and three dimensional.

17 . The method of claim 13 , wherein receiving comprises receiving the instruction having an immediate that indicates the dimensionality of the multi-dimensional space.

18 . The method of claim 13 , wherein receiving comprises receiving the instruction having an opcode that indicates the dimensionality of the multi-dimensional space.

19 . The method of claim 13 , wherein receiving comprises receiving the instruction having at least two bits that are able to indicate the given dimension as being any one of at least three different dimensions.

20 . The method of claim 13 , further comprising generating the Morton coordinates of the result packed data operand without de-interleaving bits of the Morton coordinates of the source packed data operand that correspond to different dimensions.

21 . A system to process instructions comprising:
an interconnect; a processor coupled with the interconnect, the processor to receive an instruction that is to indicate a source packed d

Assignees

• Intel Corp

Inventors

• Evans Arnold Kerry
• Ould-Ahmed-Vall Elmoustapha

Classifications

• G06F9/30032

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

• G06F9/30038

  using a mask · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/30098

  Register arrangements · CPC title

• G06F9/30025 Primary

  Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion · CPC title