Method and circuit for reducing current surge

Patent metadata

Field	Value
Publication number	US-2016139656-A1
Application number	US-201615003752-A
Country	US
Kind code	A1
Filing date	Jan 21, 2016
Priority date	Oct 4, 2012
Publication date	May 19, 2016
Grant date	—

Abstract

Systems and methods are provided for reducing surge current in power gated designs. In one aspect, a storage capacitor supplies a portion of the current used to power up a circuit. The storage capacitor may be charged from a power supply or other source. When the circuit is to be powered up, the circuit is connected to the power supply and the storage capacitor. As a result, current is supplied to the circuit from the power supply and the storage capacitor to power up the circuit. Because a portion of the current used to power up the circuit is supplied from the storage capacitor, the amount of current needed from the power supply to power up the circuit can be reduced, thereby reducing current surge through the power supply. The storage capacitor may be shared by multiple circuits.

First claim

What is claimed is:

1 . A power system, comprising:
a first power switch operable to connect a first circuit to a power supply; a second power switch operable to selectively connect a second circuit to the power supply or another power supply; a storage capacitor; a first capacitor switch operable to connect the storage capacitor to a charge source; a second capacitor switch operable to connect the storage capacitor to the first circuit; a third capacitor switch operable to connect the storage capacitor to the second circuit; and a power controller configured to:
turn on the first capacitor switch to charge the storage capacitor from the charge source;
turn off the first capacitor switch after the storage capacitor is charged,
when the first circuit is to be powered up, turn on the first power switch and the second capacitor switch to supply current to the first circuit from the charge source and the storage capacitor, and
when the second circuit is to be powered up, turn on the second power switch and the third capacitor switch to supply current to the second circuit from the respective power supply or the other power supply and the storage capacitor.

2 . The power system of claim 1 , wherein, the power controller is configured to turn off the first power switch when the first circuit is to be turned off or placed in a standby mode.

3 . The power system of claim 1 , wherein, the power controller is configured to turn off the second power switch when the second circuit is to be turned off or placed in a standby mode.

4 . The power system of claim 1 , wherein the first power switch has an adjustable resistance, and the power controller is configured to initially set the resistance of the first power switch to a first resistance when the first circuit is to be powered up, and, after a time delay, to set the resistance of the first power switch to a second resistance, the second resistance being lower than the first resistance.

5 . The power system of claim 1 , wherein the second power switch has an adjustable resistance, and the power controller is configured to initially set the resistance of the second power switch to a third resistance when the second circuit is to be powered up, and, after a time delay, to set the resistance of the second power switch to a fourth resistance, the fourth resistance being lower than the third resistance.

6 . The power system of claim 1 , wherein the first circuit comprises a memory, and the second circuit comprises logic.

7 . The power system of claim 6 , wherein the first circuit is to be powered up from a memory retention voltage to a voltage of the power supply, the memory retention voltage being lower than the voltage of the power supply.

8 . The power system of claim 1 , wherein the charge source comprises the power supply.

9 . A method for managing power provision to a circuit, the method comprising:
providing:
a first power switch operable to connect a first circuit to a first power supply;
a second power switch operable to selectively connect a second circuit to one of the first power supply or a second power supply;
a storage capacitor;
a first capacitor switch operable to connect the storage capacitor to a charge source;
a second capacitor switch operable to connect the storage capacitor to the first circuit;
a third capacitor switch operable to connect the storage capacitor to the second circuit; and
a power controller configured to:
turn on the first capacitor switch to charge the storage capacitor from the charge source;
turn off the first capacitor switch after the storage capacitor is charged,
when the first circuit is to be powered up, turn on the first power switch and the second capacitor switch to supply current to the first circuit from the charge source and the storage capacitor, and
when the second circuit is to be powered up, turn on the second power switch and the third capacitor switch to supply current to the second circuit from the respective first power supply or the second power supply and the storage capacitor.

10 . The method of claim 9 , further comprising configuring the power controller to turn off the first power switch when the first circuit is to be turned off or placed in a standby mode.

11 . The method of claim 9 , further comprising configuring the power controller to turn off the second power switch when the second circuit is to be turned off or placed in a standby mode.

12 . The method of claim 9 , wherein the first power switch has an adjustable resistance, and the method further comprises configuring the power controller to initially set the resistance of the first power switch to a first resistance when the first circuit is to be powered up, and, after a time delay, to set the resistance of the first power switch to a second resistance, the second resistance being lower than the first resistance.

13 . The method of claim 9 , wherein the second power switch has an adjustable resistance, and the method further comprises configuring the power controller to initially set the resistance of the second power switch to a third resistance when the second circuit is to be powered up, and, after a time delay, to set the resistance of the second power switch to a fourth resistance, the fourth resistance being lower than the third resistance.

14 . The method of claim 9 , wherein the first circuit comprises a memory, and the second circuit comprises logic.

15 . The method of claim 14 , wherein the memory is to be powered up from a memory retention voltage to a voltage of the power supply, the memory retention voltage being lower than the voltage of the power supply.

16 . The method of claim 9 , wherein the charge source comprises the first or the second power supply.

17 . An integrated circuit, comprising:
memory connectable to a first power supply via a first power switch; a logic circuit selectively connectable to the first power supply or a second power supply via a second power switch; a storage capacitor; a first capacitor switch operable to connect the storage capacitor to a charge source; a second capacitor switch operable to connect the storage capacitor to the memory; a third capacitor switch operable to connect the storage capacitor to the logic circuit; and a power controller configured to:
turn on the first capacitor switch to charge the storage capacitor from the charge source;
turn off the first capacitor switch after the storage capacitor is charged,
when the memory is to be powered up, turn on the first power switch and the second capacitor switch to supply current to the memory from the charge source and the storage capacitor, and
when the logic circuit is to be powered up, turn on the second power switch and the third capacitor switch to supply current to the logic circuit from the respective first power supply or the second power supply and the storage capacitor.

18 . The integrated circuit of claim 17 , wherein:
the power controller is configured to turn off the first power switch when the memory is to be turned off or placed in a standby mode, and the power controller is configured to turn off the second power switch when the logic circuit is to be turned off or placed in a standby mode.

19 . The integrated circuit of claim 17 , wherein the first power switch has an adjustable resistance, and the power controller is configured to initially set the resistance of the first power switch to a first resistance when the memory is to be powered up, and, after a time delay,

Assignees

• Broadcom Corp

Inventors

• Upputuri Bharath
• Kauffmann Bruce
• Bloker Ray

Classifications

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• G06F1/3287 Primary

  by switching off individual functional units in the computer system · CPC title

• G11C5/063 Primary

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• H03K19/0016

  by using a control or a clock signal, e.g. in order to apply power supply · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title