Package structure and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-2016135299-A1
Application number	US-201514801173-A
Country	US
Kind code	A1
Filing date	Jul 16, 2015
Priority date	Nov 10, 2014
Publication date	May 12, 2016
Grant date	—

Abstract

A method of fabricating a package structure is provided, including forming a plurality of openings by removing a portion of the material on one side of a conductive layer, forming an insulating material as an insulating layer in the openings, removing a portion of the material on the other side of the conductive layer to serve as a wiring layer, disposing an electronic component on the wiring layer, and forming an encapsulating layer to cover the electronic component, thereby allowing the single wiring layer to be connected to the electronic component on one side and connected to solder balls on the other side thereof to shorten the signal transmission path. The present invention further provides a package structure thus fabricated.

First claim

What is claimed is:

1 . A package structure, comprising:
an insulative layer having opposing first and second surfaces; a wiring layer embedded in the insulative layer and having a first side that is exposed from the first surface of the insulative layer and a second side opposing the first side and attached to the second surface of the insulative layer; at least one electronic component mounted on the second side of the wiring layer and electrically connected to the wiring layer; and an encapsulating layer formed on the second side of the wiring layer and the second surface of the insulative layer and encapsulating the electronic component.

2 . The package structure of claim 1 , wherein the second side of the wiring layer is electrically connected to the electronic component, and the first side of the wiring layer is defined to have a plurality of conductive pads thereon.

3 . The package structure of claim 1 , wherein the first side of the wiring layer is flush with the first surface of the insulative layer.

4 . The package structure of claim 1 , wherein the electronic component is an active component, a passive component, or a combination thereof.

5 . The package structure of claim 1 , wherein the electronic component is electrically connected to the wiring layer in a flip-chip manner.

6 . The package structure of claim 1 , further comprising a plurality of conductive elements formed on the first surface of the insulative layer and electrically connected to the first side of the wiring layer.

7 . A method of fabricating a package structure, comprising:
providing a conductive layer having opposing first and second sides; removing a portion of the first side of the conductive layer to form a plurality of openings on the first side of the conductive layer; forming an insulative material in the openings, allowing the insulative material to be an insulative layer that has a first surface, from which the first side of the conductive layer is exposed, and a second surface opposing the first surface; removing a portion of the second side of the conductive layer to allow the conductive layer to serve as a wiring layer, with the second surface of the insulative layer exposed from the second side of the wiring layer; disposing on the second side of the wiring layer at least one electronic component that is electrically connected to the wiring layer; and forming on the second side of the wiring layer and the second surface of the insulative layer an encapsulating layer that encapsulates the at least one electronic component.

8 . The method of claim 7 , wherein the second side of the wiring layer is electrically connected to the electronic component, and the first side of the wiring layer is defined to have a plurality of conductive pads thereon.

9 . The method of claim 7 , wherein the first side of the wiring layer is flush with the first surface of the insulative layer.

10 . The method of claim 7 , wherein the electronic component is an active component, a passive component, or a combination thereof.

11 . The method of claim 7 , wherein the electronic component is electrically connected to the wiring layer in a flip-chip manner.

12 . The method of claim 7 , further comprising forming on the first surface of the insulative layer a plurality of conductive elements that are electrically connected to the first side of the wiring layer.

13 . A method of fabricating a package structure, comprising:
providing a conductive layer having opposing first and second sides; removing a portion of the first side of the conductive layer to form a plurality of openings on the first side of the conductive layer; forming an insulative layer to completely encapsulate the first side of the conductive layer, the insulative layer having opposing first and second surfaces; removing a portion of the insulative layer, with the first side of the conductive layer exposed from the first surface of the insulative layer; removing a portion of the second side of the conductive layer to allow the conductive layer to serve as a wiring layer, with the second surface of the insulative layer exposed from the second side of the conductive layer; disposing on the second side of the conductive layer at least one electronic component that is electrically connected to the conductive layer; and forming on the second side of the conductive layer and the second surface of the insulative layer an encapsulating layer that encapsulates the electronic components.

Assignees

• Phoenix Pioneer Technology Co Ltd

Inventors

• Hsu Shih-Ping
• Liu Chin-Wen
• Wu Tang-I
• Hu Shu-Wei

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title