System and Method for Providing an Ethernet Interface

Patent metadata

Field	Value
Publication number	US-2016134671-A1
Application number	US-201614995544-A
Country	US
Kind code	A1
Filing date	Jan 14, 2016
Priority date	Dec 11, 2006
Publication date	May 12, 2016
Grant date	—

Abstract

An apparatus is provided that includes communication channels, and m communication media interfaces, and v virtual lanes. V is a positive integer multiple of the least common multiple of m and n. An information stream is transferred into data and alignment blocks striped across all of the v virtual lanes, the blocks being communicated from the virtual lanes onto the communication channels. The blocks are received on the communication channels. Each of the communication channels transmits a different portion of the blocks striped across all of the v virtual lanes.
In more particular embodiments, v>=n>=m. The communication media interfaces can be electrical and optical. Each of the communication channels can include a SerDes interface operating at least 5 Gigabits per second. Furthermore, each of the m communication media interfaces is configured to transmit a different stream of information over a single optical fiber.

First claim

1 - 28 . (canceled)

29 . A system, comprising:
memory comprising logic; and one or more processors that are configured, when executing the logic, to: receive a first information stream; transform the first information stream into a plurality of data blocks; and multiplex the plurality of data blocks of the first information stream onto a plurality of communication channels using one or more alignment blocks indicating alignments of the plurality of data blocks within the first information stream.

30 . The system of claim 29 , wherein multiplexing the plurality of data blocks of the first information stream onto a plurality of communication channels using one or more alignment blocks comprises distributing the data blocks onto the plurality of communication channels round robin.

31 . The system of claim 30 , wherein the one or more processors is further configured, when executing the logic, to insert the alignment blocks onto the plurality of communication channels periodically.

32 . The system of claim 29 , wherein each alignment block comprises 66 bits of data.

33 . The system of claim 29 , wherein each data block comprises 66 bits of data.

34 . The system of claim 29 , wherein the one or more processors are further configured, when executing the logic, to:
receive, from the plurality of communication channels, a second information stream comprising a plurality of data blocks and one or more alignment blocks; and de-multiplex the data blocks of the second information stream using the one or more alignment blocks of the second information stream.

35 . The system of claim 29 , wherein the first information stream comprises an aggregate of a plurality of frame streams.

36 . The system of claim 35 , wherein the first information stream has a data rate of 100 Gpbs, and each of the plurality of frame stream has a data rate less than 100 Gpbs.

37 . A method, comprising:
receiving a first information stream; transforming the first information stream into a plurality of data blocks; and multiplexing the plurality of data blocks of the first information stream onto a plurality of communication channels using one or more alignment blocks indicating alignments of the plurality of data blocks within the first information stream.

38 . The method of claim 37 , wherein multiplexing the plurality of data blocks of the first information stream onto a plurality of communication channels using one or more alignment blocks comprises distributing the data blocks onto the plurality of communication channels round robin.

39 . The method of claim 38 , wherein the one or more processors is further configured, when executing the logic, to insert the alignment blocks onto the plurality of communication channels periodically.

40 . The method of claim 37 , wherein each alignment block comprises 66 bits of data.

41 . The method of claim 37 , wherein each data block comprises 66 bits of data.

42 . The method of claim 37 , further comprising:
receiving, from the plurality of communication channels, a second information stream comprising a plurality of data blocks and one or more alignment blocks; and de-multiplexing the data blocks of the second information stream using the one or more alignment blocks of the second information stream.

43 . The method of claim 37 , wherein the first information stream comprises an aggregate of a plurality of frame streams.

44 . The method of claim 43 , wherein the first information stream has a data rate of 100 Gpbs, and each of the plurality of frame stream has a data rate less than 100 Gpbs.

45 . A computer readable medium including computer code such that the code is operable, when executed, to:
receive a first information stream; transform the first information stream into a plurality of data blocks; and multiplex the plurality of data blocks of the first information stream onto a plurality of communication channels using one or more alignment blocks indicating alignments of the plurality of data blocks within the first information stream.

46 . The medium of claim 45 , wherein multiplexing the plurality of data blocks onto a plurality of communication channels using one or more alignment blocks comprises distributing the data blocks onto the plurality of communication channels round robin.

47 . The medium of claim 46 , wherein the one or more processors is further configured, when executing the logic, to insert the alignment blocks onto the plurality of communication channels periodically.

48 . The medium of claim 45 , wherein each alignment block comprises 66 bits of data.

49 . The medium of claim 45 , wherein each data block comprises 66 bits of data.

50 . The medium of claim 45 , wherein the one or more processors are further configured, when executing the logic, to:
receive, from the plurality of communication channels, a second information stream comprising a plurality of data blocks and one or more alignment blocks; and de-multiplex the data blocks of the second information stream using the one or more alignment blocks of the second information stream.

51 . The medium of claim 45 , wherein the first information stream comprises an aggregate of a plurality of frame streams.

52 . The medium of claim 51 , wherein the first information stream has a data rate of 100 Gpbs, and each of the plurality of frame stream has a data rate less than 100 Gpbs.

Assignees

• Cisco Tech Inc

Inventors

• Gustlin Mark A
• Trainin Oded
• Della Chiesa Luca

Classifications

• H04L47/10

  Flow control; Congestion control · CPC title

• H04L65/61

  for supporting one-way streaming services, e.g. Internet radio · CPC title

• H04L47/13 Primary

  in a LAN segment, e.g. ring or bus · CPC title

• H04L65/4069 Primary

  Electricity · mapped topic

• H04L49/352

  Gigabit ethernet switching [GBPS] · CPC title