Non-transparent bridge method and apparatus for configuring high-dimensional pci-express networks

Patent metadata

Field	Value
Publication number	US-2016134564-A1
Application number	US-201414536516-A
Country	US
Kind code	A1
Filing date	Nov 7, 2014
Priority date	Nov 7, 2014
Publication date	May 12, 2016
Grant date	—

Abstract

The descriptions presented herein include explanation of high-dimensional PCI-Express (PCIe) network implementations. The new approaches can facilitate utilization of an efficient protocol (e.g., PCIe, etc.) while enabling implementation of various characteristics and features (e.g., characteristics and features similar to a fat-tree topology, CLOS topology, 2D and 3D topologies, etc.) that would otherwise not be compatible with the protocol. For example, implementation of alternative paths can be enabled and utilized while maintaining compliance with a protocol (e.g., PCIe, etc.) that would otherwise not be compatible with the use of alternative paths. The alternative paths can facilitate flexible topology implementation and network domain scaling while enabling improved communication latency. In one embodiment, presented systems and methods facilitate utilization of a non-transparent bridge circuit configured as an end-point with respect to communications from at least one device while facilitating transmission of the communications on to at least one other device.

First claim

1 . A non-transparent bridge circuit for communicating information in a PCIe network comprising a plurality of switches and a plurality of end-point devices, the non-transparent bridge circuit comprising:
a first network connection connected to a first switch in a first tree branch of the PCIe network and a second network connection connected to a second switch in a second tree branch of the PCIe network, wherein the non-transparent bridge circuit is assigned a first range of addresses with respect to the first switch and a second range of addresses with respect to the second switch; a processing circuit; and a memory that stores information for the processing circuit; the processing circuit being configured to: receive a first data packet from the first switch, the first data packet includes a first payload portion and a first destination address that is within the first range of addresses assigned to the non-transparent bridge; translate the first destination address to a first translated destination address, wherein the first translated destination address belongs to an endpoint device in the second tree branch and connected to the second switch; generate a first modified data packet including the first payload portion and the first translated destination address; and forward the first modified data packet to the second switch for delivery to the endpoint device in the second tree branch.

2 . The non-transparent bridge circuit of claim 1 , in which the processor is further configured to:
receive a second data packet from the second switch, the second data packet includes a second payload portion and a second destination address that is within the second range of addresses assigned to the non-transparent bridge; translate the second destination address to a second translated destination address, wherein the second translated destination address belongs to another endpoint device in the first tree branch and connected to the first switch; generate a modified data packet including the second payload portion and the second translated destination address; and forward the second modified data packet to the first switch for delivery to the endpoint device in the first tree branch.

3 . The non-transparent bridge circuit of claim 1 , in which the memory stores an address translation table that maps the first destination address to the first translated destination address.

4 . The non-transparent bridge circuit of claim 3 , in which a single entry in the address translation table is utilized to store the first destination address contained in the first data packet.

5 . The non-transparent bridge circuit of claim 1 , in which forwarding the modified data packet to the second switch bypasses an intervening third switch in the second branch and remains PCIe compliant.

6 . The non-transparent bridge circuit of claim 1 , wherein the non-transparent bridge circuit is a separate entity.

7 . The non-transparent bridge circuit of claim 1 , wherein the non-transparent bridge circuit is incorporated in a fourth one of the plurality of switches.

8 . A method for transmitting data packets via a non-transparent bridge circuit in a PCIe compliant network including a plurality of switches and endpoints coupled to the non-transparent bridge circuit, the method comprises:
receiving in a processing component of the non-transparent bridge circuit a data packet from a first one of the plurality of switches in the PCIe compliant network, the data packet includes a first address that is within one of a pair of address ranges associated with the non-transparent bridge circuit; replacing the first address in the data packet with a second address to form a modified data packet, the second address is associated with a second one of the switches included in the plurality of switches in the PCIe compliant network; and forwarding the modified data packet from the processing component to the second switch via a first data path between the first switch and the second switch, bypassing an intervening third switch in a second data path connected to the first one of the plurality of switches and the second one of the plurality of switches.

9 . The method of claim 8 enabling at least one alternative in which the first data path is at least one hop less than the second data path in the PCIe compliant network.

10 . The method of claim 8 enabling at least one alternative further comprising mapping the first address to the second address, utilizing the mapping to translate the first address with the second address, and generating the modified data packet by the replacing of the first address in the data packet with the second address.

11 . The method of claim 10 enabling at least one alternative in which the mapping prevents data packets from being transmitted through a loop transmission path formed at least in part by the first data path and the second data path.

12 . The method of claim 8 enabling at least one alternative in which the first data path and second data path enable multi-path routing in the PCIe compliant network.

13 . The method of claim 8 enabling at least one alternative in which the size of the one of the pair of address ranges is equal to or larger than the difference between a beginning address and an end address allocated to a plurality of resources coupled to the non-transparent bridge, the second switch is included in the plurality of resources.

14 . The method of claim 8 enabling at least one alternative in which the size of the one of the pair of address ranges is equivalent to the sum of addresses allocated to a plurality of resources coupled to the non-transparent bridge, the second switch is included in the plurality of resources.

15 . The method of claim 8 enabling at least one alternative in which the length of one of the pair of address ranges is equivalent to the length of addresses assigned to resources on one communication side of the non-transparent bridge and the length of the of another one of the pair of address ranges is equivalent to the length of addresses assigned to resources on an opposite communication side of the non-transparent bridge.

16 . A PCIe compliant network system for communicating information though components configured in a topology that includes multiple different paths between two switches, the PCIe compliant network system comprising:
a plurality of switch devices coupled together to form a PCIe compliant tree topology with a plurality of branches; a plurality of end point devices that are coupled to the ends of the plurality of branches; and a non-transparent bridge exposed to a first one of the plurality of switches by a first range of addresses assigned to the non-transparent bridge and exposed to a second one of the plurality of switches by a second range of addresses assigned to the non-transparent bridge, the non-transparent bridge communicating information in the PCIe compliant network between the first one of the plurality of switches and second one of the plurality of switches by translating a destination address within the first range of addresses assigned to the non-transparent bridge to a translated destination address associated with a resource coupled to the second one of the plurality of switches and translating a destination addresses within the second range of addresses assigned to the non-transparent bridge to a translated destination address associated with a resource coupled to the first one of the plurality of switches.

17 . The PCIe compliant network system of claim 16 , in which the non-transparent bridge

Assignees

• Futurewei Technologies Inc

Inventors

• Egi Norber
• Lasater Robert
• Shi Guangyu

Classifications

• H04L12/4625

  Single bridge functionality, e.g. connection of two networks over a single bridge · CPC title

• H04L45/24

  Multipath · CPC title

• H04L12/4015

  by scheduling the transmission of messages at the communication node · CPC title

• H04L49/15

  Interconnection of switching modules · CPC title

• H04L41/12

  Discovery or management of network topologies · CPC title