Fec coding identification

Patent metadata

Field	Value
Publication number	US-2016134394-A1
Application number	US-201414536303-A
Country	US
Kind code	A1
Filing date	Nov 7, 2014
Priority date	Oct 16, 2012
Publication date	May 12, 2016
Grant date	—

Abstract

The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide techniques for transceivers to quickly identify FEC mode used in data communication. A transmitting transceiver embeds FEC mode information in a designated field of an alignment marker. The receiving transceiver acknowledges the receipt of the FEC mode information and processes the incoming data accordingly. There are other embodiments as well.

First claim

What is claimed is:

1 . A system for providing coding identification, the system comprising:
a first transceiver comprising a first alignment module, a first FEC module, and a pattern generator, the first transceiver being configured to generate at least a first data stream and a plurality of alignment markers, the plurality of alignment markers including a first alignment marker and a second alignment marker, the first alignment marker comprising a device message, the first alignment marker comprising an FEC mode message; a second transceiver comprising a second alignment module and a second FEC module, the second transceiver being configured to process the plurality of alignment markers and the first data stream; wherein: the first FEC module encodes the first data stream using a first FEC mode; the FEC mode message indicates the first FEC mode; the second transceiver determines the first FEC mode from the second alignment marker; the second transceiver processes the first data stream using the first FEC mode.

2 . The system of claim 1 wherein first alignment marker comprises a BIP field, the device message being stored at the BIP field.

3 . The system of claim 1 wherein the alignment module is configured to align and process data received from two or more data channels.

4 . The system of claim 1 wherein the first FEC mode is associated with BCH code or RS code.

5 . The system of claim 1 wherein the pattern generator is configured to generate PAM symbols.

6 . The system of claim 1 wherein the second transceiver sends an acknowledgement message to the first transceiver upon receiving the first alignment marker.

7 . The system of claim 1 wherein the second transceiver processes a second data stream using a second FEC mode in response to receiving a third alignment marker.

8 . The system of claim 1 wherein the first transceiver further comprises a PAM modulator.

9 . The system of claim 1 wherein the second transceiver further comprises a analog-to-digital converter.

10 . A transceiver device comprising:
an input interface for processing incoming data from a plurality of channels; an alignment module for generating a first data stream based on the incoming data received from the plurality of channels, the first data stream being separated by a plurality of alignment markers, the first plurality of alignment markers including a first alignment marker and a second alignment marker; an FEC module being configured to encode the first data stream in a first FEC mode; a processing module configured to generate a second data stream and to embed a first device message in the first alignment marker and a first FEC mode message in the second alignment marker; and an output interface for transmitting the first data stream and the plurality of alignment markers to a receiving entity.

11 . The device of claim 10 wherein the processing module embeds a second device message in a third alignment marker if an acknowledgement message is not received from the receiving entity within a predetermined period of time.

12 . The device of claim 10 the processing module embeds a second FEC mode message in a third alignment marker if an acknowledgement message is not received from the receiving entity within a predetermined period of time.

13 . The device of claim 10 the processing module embeds a second FEC mode message in a third alignment marker in response to the FEC mode operating using a second FEC mode.

14 . The device of claim 10 further comprising a PAM modulator for modulating the first data stream.

15 . The device of claim 10 wherein the incoming data is characterized by an aggregate bandwidth of at least 100 gigabits/s.

16 . The device of claim 10 wherein the processing module sets a BIP field to “0” in a third alignment marker if an acknowledgement message is not received from the receiving entity within a predetermined period of time.

17 . A transceiver device comprising:
an input data communication interface for receiving an analog data stream from a transmitting entity; an ADC module for converting the analog data stream to a data stream and a plurality of alignment markers, the plurality of alignment markers including a first alignment markers and a second alignment marker; a processing module for determining an FEC mode by processing a device message embedded at the first alignment marker and a first FEC mode message; and an FEC module for processing the data stream in accordance with the first FEC mode.

18 . The device of claim 17 wherein the FEC module is configured to processing the data stream in accordance with a second FEC mode in response to receiving a second FEC mode message embedded in a third alignment message.

19 . The device of claim 17 wherein the processing module is configured to generate an acknowledgement message for the transmitting entity in response to receiving the device message.

20 . The device of claim 17 wherein the processing module is configured to generate an acknowledgement message for the transmitting entity in response to receiving the first FEC mode message.

Assignees

• Inphi Corp

Inventors

• Tiruvur Arun
• Bhoja Sudeep

Classifications

• H04L5/0048

  Allocation of pilot signals, i.e. of signals known to the receiver (allocation of control signalling H04L5/0053; use of control signalling H04L5/0091) · CPC title

• H04L1/0061 Primary

  Error detection codes · CPC title

• H04Q2011/0088

  Signalling aspects · CPC title

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L25/03267

  with decision feedback equalisers · CPC title