Output discharge techniques for load switches

Patent metadata

Field	Value
Publication number	US-2016134283-A1
Application number	US-201514938702-A
Country	US
Kind code	A1
Filing date	Nov 11, 2015
Priority date	Nov 12, 2014
Publication date	May 12, 2016
Grant date	—

Abstract

An output discharge circuit for a load switch may include a capacitor coupled between a power rail of the output discharge circuit and a ground lead, and a diode coupled between a power input of the output discharge circuit and the power rail. The output discharge circuit may charge the capacitor via a current path formed by the diode while power is being supplied to the load switch. When the power supply to the output discharge circuit is turned off, the diode may prevent the capacitor from discharging through the current path, and the stored charge on the capacitor may be used to power the output discharge switch for a period of time after the power supply has been turned off. In this way, the output discharge circuit may continue to discharge the output of the load switch even when power is no longer being supplied to the load switch.

First claim

What is claimed is:

1 . An integrated circuit comprising:
an input voltage lead; an output voltage lead; a pass transistor coupled between the input voltage lead and the output voltage lead; and an output discharge circuit including:
a power input;
a control input;
a first transistor coupled between the output voltage lead and a ground lead, the first transistor having a control electrode;
a diode having an anode coupled to the power input;
a capacitor coupled between a cathode of the diode and the ground lead;
a resistor coupled between the cathode of the diode and the control electrode of the first transistor; and
a second transistor coupled between the control electrode of the first transistor and the ground lead, the second transistor having a control electrode coupled to the control input of the output discharge circuit.

2 . The integrated circuit of claim 1 , wherein the capacitor is a first capacitor, the diode is a first diode, the transistor is a first transistor, and the integrated circuit further comprises:
a switch enable lead; and a control circuit including:
a power input;
a third transistor coupled between a gate electrode of the pass transistor and the control input of the output discharge circuit, the third transistor having a control electrode;
a fourth transistor coupled between the control input of the output discharge circuit and the ground lead;
a buffer having an input coupled to the switch enable lead, an output coupled to a control electrode of the fourth transistor, and a power rail coupled to the control electrode of the third transistor;
a second capacitor coupled between the control electrode of the third transistor and the ground lead; and
a second diode having an anode coupled to the power input of the control circuit, and a cathode coupled to the control electrode of the third transistor and to the power rail of the buffer.

3 . An integrated circuit comprising:
an input voltage lead; an output voltage lead; a pass transistor coupled between the input voltage lead and the output voltage lead; and an output discharge circuit coupled between the output voltage lead and a ground lead, the output discharge circuit including:
a power input;
a diode having an anode coupled to the power input; and
a capacitor coupled between a cathode of the diode and the ground lead.

4 . The integrated circuit of claim 3 , wherein the output discharge circuit further includes:
a control input; a switch coupled between the output voltage lead and the ground lead, the switch having a control electrode; and a buffer having an input coupled to the control input of the output discharge circuit, an output coupled to the control electrode of the switch, and a power rail coupled to the cathode of the diode.

5 . The integrated circuit of claim 4 , wherein the buffer is an inverter.

6 . The integrated circuit of claim 5 , wherein the inverter is an n-type metal-oxide semiconductor (NMOS) inverter.

7 . The integrated circuit of claim 4 , wherein the buffer is a non-inverting buffer.

8 . The integrated circuit of claim 4 , further comprising:
a control circuit coupled between a gate electrode of the pass transistor and the control input of the output discharge circuit.

9 . The integrated circuit of claim 8 , wherein the capacitor is a first capacitor, the diode is a first diode, and the control circuit includes:
a reference voltage input; a transistor coupled between the gate electrode of the pass transistor and the control input of the output discharge circuit, the transistor having a control electrode; a second capacitor coupled between the control electrode of the transistor and the ground lead; and a second diode having an anode coupled to the reference voltage input, and a cathode coupled to the control electrode of the transistor.

10 . The integrated circuit of claim 9 , wherein the reference voltage input is coupled to the input voltage lead.

11 . The integrated circuit of claim 10 , further comprising:
a bias voltage lead; a charge pump circuit coupled to the bias voltage lead; and a gate driver circuit having a power input coupled to the charge pump circuit, and an output coupled to the gate of the pass transistor, wherein the control circuit further includes a third diode having an anode coupled to the bias voltage lead, and a cathode coupled to the control electrode of the transistor.

12 . The integrated circuit of claim 8 , wherein the control circuit includes:
a gate electrode discharge circuit coupled between the control input of the output discharge circuit and the ground lead.

13 . The integrated circuit of claim 12 , wherein the capacitor is a first capacitor, the diode is a first diode, the integrated circuit further comprises a switch enable lead, the gate electrode discharge circuit includes a transistor coupled between the control input of the output discharge circuit and the ground, and the control circuit further includes:
a power input; a buffer having an input coupled to the switch enable lead, an output coupled to a control electrode of the transistor, and a power rail; a second capacitor coupled between the power rail of the buffer and the ground lead; and a second diode having an anode coupled to the power input of the control circuit, and a cathode coupled to the power rail of the buffer.

14 . The integrated circuit of claim 13 , wherein the power input of the control circuit is coupled to the input voltage lead.

15 . The integrated circuit of claim 14 , further comprising:
a bias voltage lead; a charge pump circuit coupled to the bias voltage lead; and a gate driver circuit having a power input coupled to the charge pump circuit, and an output coupled to a gate of the pass transistor, wherein the control circuit further includes a third diode having an anode coupled to the bias voltage lead, and a cathode coupled to the power rail of the buffer.

16 . The integrated circuit of claim 3 , wherein the output discharge circuit further includes:
a control input; a switch coupled between the output voltage lead and the ground lead, the switch having a control electrode; a resistive component coupled between the cathode of the diode and the control electrode of the switch; and a transistor coupled between control electrode of the switch and the ground lead, the transistor having a control electrode coupled to the control input of the output discharge circuit.

17 . The integrated circuit of claim 3 , wherein the power input of the output discharge circuit is coupled to the input voltage lead.

18 . The integrated circuit of claim 3 , further comprising:
a bias voltage lead; a charge pump circuit coupled to the bias voltage lead; and a gate driver circuit having a power input coupled to the charge pump circuit, and an output coupled to a gate of the pass transistor, wherein the power input of the output discharge circuit is coupled to the bias voltage lead.

19 . The integrated circuit of claim 18 , wherein the power input of the output discharge circuit is a first power input, the diode is a first diode, and the output discharge circuit further includes:
a second power input; a second diode having an anode coupled to the second power input; and wherein a cathode of the second diode is coupled to the capacitor and to the cathode of the first diode.

20 . A method comprising:
charging, via a current path, a capacitor coupled between a power rail of a buffer and a

Assignees

• Texas Instruments Inc

Inventors

• Dhamdhere Vikrant
• Schulmeyer Kyle
• Rahman Md Abidur

Classifications

• H01L27/0629

  Electricity · mapped topic

• H01L23/50

  Electricity · mapped topic

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H01L23/5286

  Electricity · mapped topic

• H03K17/687 Primary

  the devices being field-effect transistors · CPC title