Bias circuit and power amplifier having the same

Patent metadata

Field	Value
Publication number	US-2016134245-A1
Application number	US-201514886804-A
Country	US
Kind code	A1
Filing date	Oct 19, 2015
Priority date	Nov 10, 2014
Publication date	May 12, 2016
Grant date	—

Abstract

A bias circuit providing different bias voltages depending on a power mode through a simple circuit, and a power amplifier having the same are provided. The bias circuit and the power amplifier include a bias setting unit configured to vary a voltage level of a control signal controlling a bias voltage according to an operation of a first transistor being switched-off in a high power mode and switched-on in a low power mode. A bias supplying unit includes a bias supplying transistor switched based on the control signal, to supply the bias voltage having a voltage level according to a switching operation of the bias supplying transistor.

First claim

What is claimed is:

1 . A bias circuit, comprising:
a bias setting unit configured to vary a voltage level of a control signal controlling a bias voltage according to an operation of a first transistor being switched-off in a high power mode and switched-on in a low power mode; and a bias supplying unit comprising a bias supplying transistor switched based on the control signal, to supply the bias voltage having a voltage level according to a switching operation of the bias supplying transistor.

2 . The bias circuit of claim 1 , wherein the bias setting unit comprises:
a control signal providing unit configured to provide the control signal having a level set according to a voltage level of a reference power; and a control signal varying unit comprising the first transistor and a first resistor connected to a collector of the first transistor, wherein the first transistor is switched-off in the high power mode to maintain the signal level of the control signal and is switched-on in the low power mode to reduce the signal level of the control signal.

3 . The bias circuit of claim 2 , wherein the control signal providing unit comprises a second transistor, a third transistor, a second resistor, and a third resistor,
the signal level of the control signal is determined according to a sum of a base-emitter voltage of the second transistor and a base-emitter voltage of the third transistor, a resistance value of the second resistor determines a voltage level of the base-emitter voltage of the second transistor, and a resistance value of the third resistor determines a voltage level of the base-emitter voltage of the third transistor.

4 . The bias circuit of claim 3 , wherein the control signal providing unit further includes a capacitor stabilizing the reference power,
the first transistor comprises a base receiving a power mode signal having information regarding the power mode through a fourth resistor, and an emitter connected to a ground, the second transistor comprises an emitter connected to the ground through the second resistor, and a base connected to the capacitor to be supplied with the reference power stabilized by the capacitor according to switching-on or switching-off of the third transistor, and the third transistor has an emitter connected to the ground, a collector receiving the reference power through the third resistor, and a base connected to the emitter of the second transistor.

5 . A power amplifier, comprising:
a bias circuit comprising a bias setting unit varying a voltage level of a control signal controlling a bias voltage based on a first transistor being switched-off in a high power mode and switched-on in a low power mode, and a bias supplying unit comprising a bias supplying transistor switched according to the control signal from the bias setting unit, and configured to supply the bias voltage having a voltage level according to a switching operation of the bias supplying transistor; and an amplifying unit configured to receive the bias voltage from the bias circuit to amplify a power level of an input signal.

6 . The power amplifier of claim 5 , further comprising:
an input matching circuit configured to match impedance of a signal transfer path between an input signal terminal from which the input signal is input, and the amplifying unit.

7 . The power amplifier of claim 5 , further comprising:
an output matching circuit configured to match impedance of a signal transfer path between an output signal terminal to which an output signal amplified by the amplifying unit is output, and the amplifying unit.

8 . The power amplifier of claim 5 , wherein the bias circuit reduces a voltage level of the bias voltage at a time of the low power mode to reduce current consumption of the amplifying unit.

9 . The power amplifier of claim 5 , wherein the bias setting unit includes:
a control signal providing unit configured to provide the control signal having a level set according to a voltage level of received reference power; and a control signal varying unit comprising the first transistor and a first resistor connected to a collector of the first transistor, the first transistor being switched-off in the high power mode to maintain the signal level of the control signal and being switched-on in the low power mode to reduce the signal level of the control signal.

10 . The power amplifier of claim 9 , wherein the control signal providing unit comprises a second transistor, a third transistor, a second resistor, and a third resistor,
the signal level of the control signal is determined according to a sum of a base-emitter voltage of the second transistor, and a base-emitter voltage of the third transistor, a resistance value of the second resistor determines a voltage level of the base-emitter voltage of the second transistor, and a resistance value of the third resistor determines a voltage level of the base-emitter voltage of the third transistor.

11 . The power amplifier of claim 10 , wherein the control signal providing unit further comprises a capacitor stabilizing the reference power,
the first transistor comprises a base receiving a power mode signal having information regarding the power mode through a fourth resistor, and an emitter connected to a ground, the second transistor comprises an emitter connected to the ground through the second resistor, and a base connected to the capacitor to be supplied with the reference power stabilized by the capacitor according to switching-on or switching-off of the third transistor, and the third transistor has an emitter connected to the ground, a collector receiving the reference power through the third resistor, and a base connected to the emitter of the second transistor.

12 . A bias circuit, comprising:
a control signal providing unit configured to provide a control signal having a signal level based on a voltage level of reference power; a control signal varying unit configured to vary the signal level of the control signal according to a power mode signal; and a bias supplying unit configured to vary a voltage level of a bias voltage based on the control signal and supply the varied voltage level of the bias voltage, wherein
in response to the power mode signal being a high power mode, the control signal varying unit is turned-off and the signal level of the control signal is maintained and applied to the bias supplying unit, and
in response to the power mode signal being a low power mode, the control signal varying unit is turned-on to receive and decrease the signal level of the control signal and transmit the control signal, as decreased, to the bias supplying unit.

13 . The bias circuit of claim 12 , wherein the reference power comprises a preset voltage level according to the high power mode or the low power mode.

14 . The bias circuit of claim 12 , wherein the control signal varying unit comprises a first transistor, a first resistor, and a fourth resistor, wherein, in response to the first transistor receiving the power mode signal as the high power mode, the first transistor is turned-off to maintain the signal level of the control signal, and the maintained signal level of the control signal is applied to a base of a bias supplying transistor of the bias supplying unit.

15 . The bias circuit of claim 12 , wherein the bias supplying unit comprises a bias supplying transistor and a resistor, wherein the bias supplying transistor is switched based on the control signal to supply the bias voltage, having the varied voltage level based on a degree of turn-on of the bias supplying tr

Assignees

• Samsung Electro Mech

Inventors

• Won Jun Goo
• Kim Youn Suk
• Tonami Yoshiyuki
• Kim Ki Joong

Classifications

• H03K17/60 Primary

  the devices being bipolar transistors (bipolar transistors having four or more electrodes H03K17/72) · CPC title

• H03F2200/18

  the bias of the gate of a FET being controlled by a control signal · CPC title

• H03F1/301

  in MOSFET amplifiers (H03F1/303, H03F1/305, H03F1/308 take precedence) · CPC title

• H03F2200/21

  Bias resistors are added at the input of an amplifier · CPC title

• H03F3/19

  with semiconductor devices only · CPC title