3d memory

Patent metadata

Field	Value
Publication number	US-2016133752-A1
Application number	US-201614987147-A
Country	US
Kind code	A1
Filing date	Jan 4, 2016
Priority date	Jan 24, 2013
Publication date	May 12, 2016
Grant date	—

Abstract

Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.

First claim

1 - 20 . (canceled)

21 . A vertical memory comprising:
a stack of memory cells, a cell of the stack comprising: a control gate having a substantially planar side; a charge storage structure having a substantially planar side; a barrier film between the charge storage structure and the control gate, the barrier film having a first substantially planar side facing the substantially planar side of the control gate and a second substantially planar side opposite the first substantially planar side and facing the substantially planar side of the charge storage structure; a first dielectric between the barrier film and the charge storage structure at the second substantially planar side; and a second dielectric between the barrier film and the control gate at the first substantially planar side of the barrier film.

22 . The memory of claim 21 , wherein each part of the second substantially planar side of the barrier film is separated from the face of the charge storage structure by a substantially equal distance.

23 . The memory of claim 21 , wherein a dimension of the charge storage structure is substantially greater than or equal to a dimension of the second substantially planar side.

24 . The memory of claim 23 , wherein the dimension of the charge storage structure substantially equal to or greater than the dimension of the barrier film comprises the dimension of the charge storage structure being substantially equal to the dimension of the barrier film.

25 . The memory of claim 21 , further comprising a pillar adjacent to the charge storage structure and wherein a dielectric is between the pillar and the charge storage structure.

26 . The memory of claim 25 , wherein the pillar comprises polysilicon, the charge storage structure comprises polysilicon, the dielectric comprises oxide, and the barrier film comprises nitride.

27 . The memory of claim 21 , wherein the stack of memory cells comprises a NAND string of memory cells.

28 . The memory of claim 21 , wherein the barrier film is entirely between a plane corresponding to a side of the charge storage structure and a plane corresponding to a side of the control gate opposing the side of the charge storage structure.

29 . The memory of claim 21 , wherein the charge storage structure and the barrier film are formed in a control gate recess adjacent to the control gate.

30 . A vertical stack of memory cells comprising a vertical pillar, wherein a cell of the stack comprises:
a charge storage structure adjacent to the pillar along a dimension, the charge storage structure having a substantially planar side; a first dielectric between the charge storage structure and the pillar; a barrier film adjacent to the charge storage structure along the dimension, the barrier film including a first substantially planar side facing the substantially planar side of the charge storage structure, the barrier film including a second substantially planar side opposite the first substantially planar side; a control gate adjacent to the dielectric and barrier film along the dimension, the control gate including a substantially planar side facing the second substantially planar side; a second dielectric between the barrier film and the charge storage structure at the first substantially planar side of the barrier film; and a third dielectric between the barrier film and the control gate at the second substantially planar side.

31 . The stack of claim 30 , wherein the charge storage structure is substantially rectangular.

32 . The stack of claim 30 , wherein the control gate comprises doped polysilicon.

33 . The stack of claim 30 , wherein the pillar comprises polysilicon, the charge storage structure comprises polysilicon, the dielectric comprises oxide, and the barrier film comprises nitride.

34 . The stack of claim 30 , wherein the stack comprises a NAND string of memory cells.

35 . The stack of claim 30 , wherein the dielectric surrounds the charge storage structure and the barrier film.

36 . The stack of claim 30 , wherein the charge storage structure and the barrier film are formed in a control gate recess.

37 . A vertical stack of memory cells, wherein a cell of the stack is formed in a control gate recess and comprises:
a charge storage structure having a substantially planar side; a barrier film including a first substantially planar side facing the substantially planar side of the charge storage structure, the barrier film including a second substantially planar side opposite the first substantially planar side; a control gate including a substantially planar side facing the second substantially planar side; a second dielectric between the barrier film and the charge storage structure at the first substantially planar side; and a third dielectric between the barrier film and the control gate at the second substantially planar side.

38 . The stack of claim 37 , wherein a dimension of the substantially planar side of the control gate is substantially equal to a corresponding dimension of the second substantially planar side of the barrier film.

39 . The stack of claim 38 , wherein the barrier film is substantially rectangular.

40 . The stack of claim 39 , wherein, in a vertical cross-section of the memory cell, a surface area of the barrier film of the cell is less than a surface area of the charge storage structure of the cell.

Assignees

• Micron Technology Inc

Inventors

• Hopkins John
• Fan Darwin Franseda
• Simsek-Ege Fatma Arzum
• Brighten James
• Mauri Aurelio Giancarlo
• Jayanti Srikant

Classifications

• H10D64/01306

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon · CPC title

• H10D30/689

  Vertical floating-gate IGFETs · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title

• H10D30/6891

  characterised by the shapes, relative sizes or dispositions of the floating gate electrode · CPC title

• H10D64/01 Primary

  Manufacture or treatment · CPC title