Method and apparatus for setting high address bits in a memory module

Patent metadata

Field	Value
Publication number	US-2016132269-A1
Application number	US-201614995145-A
Country	US
Kind code	A1
Filing date	Jan 13, 2016
Priority date	Mar 15, 2013
Publication date	May 12, 2016
Grant date	—

Abstract

Provided are a method and apparatus for setting high address bits in a memory module. A memory module controller in the memory module, having pins to communicate on a bus, determines whether high address bits are available for the memory module, uses a predetermined value for at least one high address bit with addresses communicated from a host memory controller in response to determine that the high address bits are not available to address a first address space in the memory module, and uses values communicated from the host memory controller on at least one of the pins used for the at least one high address bit in response to determine that the high address bits are available to address a second address space, wherein the second address space is larger than the first address space.

First claim

1 . An apparatus, comprising:
a memory module controller in a memory module having pins to communicate on a bus, to:
determine whether high address bits are available for the memory module;
use a predetermined value for at least one high address bit with addresses communicated from a host memory controller in response to determine that the high address bits are not available to address a first address space in the memory module; and
use values communicated from the host memory controller on at least one of the pins used for the at least one high address bit in response to determine that the high address bits are available to address a second address space, wherein the second address space is larger than the first address space.

2 . The apparatus of claim 1 , wherein the memory module controller is further to:
receive a command from the host memory controller indicating that the high address bits are available; and set a value in a register to indicate that the high address bits are available, wherein the determination of whether the high address bits are available is made by reading the value in the register.

3 . The apparatus of claim 2 , wherein the high address bits are not available based on at least one of the capabilities of the bus and an interface configuration of the memory module.

4 . The apparatus of claim 3 , wherein the high address bits are not available when the memory module has a smaller address space than supported on the bus.

5 . The apparatus of claim 4 , wherein the high address bits are not available when the memory module comprises a Small Outline Dual In-line Memory Module (SODIMM).

6 . The apparatus of claim 2 , wherein the command comprises a Mode Register Set (MRS) command, and wherein the register that is set comprises one of the mode registers set by the MRS command.

7 . The apparatus of claim 1 , wherein the memory module controller supports different addressing capabilities for different supported interface configurations on a bus and the memory module.

8 . A memory module in communication with a memory controller over a bus, comprising:
pins to communicate on the bus; memory chips to store data from host memory controller; and a memory module controller to read and write to the memory chips and to:
determine whether high address bits are available for the memory module;
use a predetermined value for at least one high address bit with addresses communicated from a host memory controller in response to determine that the high address bits are not available to address a first address space in the memory chips; and
use values communicated from the host memory controller on at least one of the ins used for the at least one high address bit in response to determine that the high address bits are available to address a second address space, wherein the second address space is larger than the first address space.

9 . The memory module of claim 8 , wherein the memory module controller is further to:
receive a command from the host memory controller indicating that the high address bits are available; and set a value in a register to indicate that the high address bits are available, wherein the determination of whether the high address bits are available is made by reading the value in the register.

10 . The memory module of claim 9 , wherein the high address bits are not available based on at least one of the capabilities of the bus and the interface configuration of the memory module.

11 . The memory module of claim 10 , wherein the high address bits are not available when the memory module has a smaller address space than supported on the bus.

12 . The memory module of claim 11 , wherein the high address bits are not available when the memory module comprises a Small Outline Dual In-line Memory Module (SODIMM).

13 . The memory module of claim 9 , wherein the command comprises a Mode Register Set (MRS) command, and wherein the register that is set comprises one of the mode registers set by the MRS command.

14 . The memory module of claim 8 , wherein the memory module controller supports different addressing capabilities for different supported interface configurations on the bus and the memory module.

15 . A system comprising:
a processor; a host memory controller in communication with the processor; a bus; at least one memory module in data communication with the host memory controller, wherein each of the at least one memory module includes:
pins to communicate on the bus;
memory chips to store data from host memory controller; and
a memory module controller to read and write to the memory chips and to:
determine whether high address bits are available for the memory module;
use a predetermined value for at least one high address bit with addresses communicated from a host memory controller in response to determining that the high address bits are not available to address a first address space in the memory chips; and
use values communicated from the host memory controller on at least one of the pins used for the at least one high address bit in response to determine that the high address bits are available to address a second address space, wherein the second address space is larger than the first address space.

16 . The system of claim 15 , wherein the memory module controller is further to:
receive a command from the host memory controller indicating that the high address bits are available; and set a value in a register to indicate that the high address bits are available, wherein the determination of whether the high address bits are available is made by reading the value in the register.

17 . The system of claim 16 , wherein the high address bits are not available based on at least one of the capabilities of the bus and an interface configuration of the memory module.

18 . An method, comprising:
determine whether high address bits are available for a memory module; use a predetermined value for at least one high address bit with addresses communicated from a host memory controller in response to determine that the high address bits are not available to address a first address space in the memory module; and use values communicated from the host memory controller on at least one pin of the memory module used for the at least one high address bit in response to determine that the high address bits are available to address a second address space, wherein the second address space is larger than the first address space.

19 . The method of claim 18 , further comprising:
receive a command from the host memory controller indicating that the high address bits are available; and set a value in a register to indicate that the high address bits are available, wherein the determination of whether the high address bits are available is made by reading the value in the register.

20 . The method of claim 19 , wherein the high address bits are not available based on at least one of the capabilities of a bus and an interface configuration of the memory module.

21 . The method of claim 20 , wherein the high address bits are not available when the memory module has fewer pins used for addressing than supported on the bus.

22 . The method of claim 21 , wherein the high address bits are not available when the memory module comprises a Small Outline Dual In-line Memory Module (SODIMM).

23 . The method of claim 19 , wherein the command comprises a Mode Register Set (MRS) co

Assignees

• Intel Corp

Inventors

• Nale Bill

Classifications

• G06F12/0813

  with a network or matrix configuration · CPC title

• G06F11/079

  Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36) · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/0638 Primary

  Organizing or formatting or addressing of data · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title