Charge pump circuit, integrated circuit, electronic device and method therefor

Patent metadata

Field	Value
Publication number	US-2016126830-A1
Application number	US-201514872146-A
Country	US
Kind code	A1
Filing date	Oct 1, 2015
Priority date	Oct 30, 2014
Publication date	May 5, 2016
Grant date	—

Abstract

A charge pump circuit for generating a negative voltage has a switched capacitor voltage inverter circuit arranged to receive at least one clock signal and generate a negative voltage therefrom; a regulation control loop providing a feedback path from the output of the switched capacitor voltage inverter circuit to a supply input of the switched capacitor voltage inverter circuit, wherein the regulation control loop has a filter arranged to filter the generated negative voltage; and an output arranged to output the filtered generated negative voltage.

First claim

What is claimed is:

1 . A charge pump circuit for generating a negative voltage comprising:
a switched capacitor voltage inverter circuit arranged to receive at least one clock signal and generate a negative voltage therefrom; a regulation control loop providing a feedback path from the output of the switched capacitor voltage inverter circuit to a supply input of the switched capacitor voltage inverter circuit, wherein the regulation control loop comprises a filter arranged to filter the generated negative voltage; and an output arranged to output the filtered generated negative voltage.

2 . The charge pump circuit of claim 1 wherein the filter comprises a higher order resistor-capacitor (RC)-based filter configured to remove clock harmonic content of the received at least one clock signal.

3 . The charge pump circuit of claim 1 wherein the filter is further arranged to separate the generated negative voltage used by the clock generator from a supply at the output of the filter.

4 . The charge pump circuit of claim 1 wherein the feedback path comprises an operational amplifier such that a first input of the operational amplifier represents an output voltage sense of the filtered negative voltage output.

5 . The charge pump circuit of claim 4 wherein the operational amplifier output is configured to control a voltage supplied to the switched capacitor voltage inverter circuit.

6 . The charge pump circuit of claim 4 wherein the regulation control loop is arranged to function in an open loop mode of operation at a start-up of the charge pump circuit to generate the negative voltage and subsequently function in a closed loop mode of operation for regulation once the operational amplifier is active.

7 . The charge pump circuit of claim 6 wherein an input voltage to the regulation control loop is set to a maximum by the operational amplifier during the start-up open loop mode of operation.

8 . The charge pump circuit of claim 4 wherein the operational amplifier within the regulation control loop is configured to provide loop stability compensation at low operational frequencies.

9 . The charge pump circuit of claim 4 further comprising a second input of the operational amplifier operably coupled to a control circuit that is arranged to maintain a constant reference voltage applied to the second input constant during a loop start up.

10 . The charge pump circuit of claim 4 wherein the switch capacitor voltage inverter comprises a plurality of MOSCAPs and the operational amplifier is configured to generate a maximum charging supply voltage to charge a number of MOSCAPs of the switch capacitor voltage inverter during a loop start up.

11 . The charge pump circuit of claim 1 further comprising an additional filter located in the feedback path and configured to sense the negative output voltage.

12 . The charge pump circuit of claim 11 wherein the additional filter is arranged to perform filtering and level shifting for a feedback loop sense of the negative output voltage.

13 . The charge pump circuit of claim 1 further comprising a clock generator configured to provide at least one clock signal to the switched capacitor voltage inverter circuit and comprising a level shifting circuit arranged to provide level-shifted charge pump clock signals.

14 . The charge pump circuit of claim 13 wherein the level shifting circuit applies an intermediate step to a regulator output voltage.

15 . The charge pump circuit of claim 13 wherein the clock generator comprises a two-phase clock generator configured to provide two clock signal phases of a generated clock to the switched capacitor voltage inverter circuit such that the charge pump circuit is arranged to provide a charge pump negative voltage output on alternate phases of the generated clock.

16 . The charge pump circuit of claim 15 wherein the two-phase clock generator is configured to provide a plurality of non-overlapping clock signals having different voltage levels.

17 . The charge pump circuit of claim 16 wherein the negative voltage output of the switched capacitor voltage inverter circuit is input to the two-phase clock generator and the two-phase clock generator uses the fed back negative voltage in a generation of a number of clock signals that traverse between the negative voltage and a voltage potential.

18 . An electronic device comprising the charge pump circuit of claim 1 .

19 . An integrated circuit comprising:
a charge pump circuit for generating a negative voltage comprising: a switched capacitor voltage inverter circuit arranged to receive at least one clock signal and generate a negative voltage therefrom; a regulation control loop providing a feedback path from the output of the switched capacitor voltage inverter circuit to a supply input of the switched capacitor voltage inverter circuit, wherein the regulation control loop comprises a filter arranged to filter the generated negative voltage; and an output arranged to output the filtered generated negative voltage.

20 . A method of generating a negative voltage using a charge pump circuit comprising a switched capacitor voltage inverter circuit, the method comprising:
providing at least one clock signal input to the switched capacitor voltage inverter circuit; generating a negative voltage by the switched capacitor voltage inverter circuit; filtering the generated negative voltage; outputting the filtered generated negative voltage; and feeding back the filtered negative voltage to set an input supply to the switched capacitor voltage inverter circuit thereby forming a regulation control loop for the charge pump circuit.

Assignees

• Mediatek Singapore Pte Ltd

Inventors

• Fowers Paul
• Collados Asensio Manel

Classifications

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H02M3/071

  adapted to generate a negative voltage output from a positive voltage source · CPC title

• H03K19/0016

  by using a control or a clock signal, e.g. in order to apply power supply · CPC title

• H02M1/36

  Means for starting or stopping converters · CPC title

• H03K19/00384

  in field effect transistor circuits · CPC title