Semiconductor device

Patent metadata

Field	Value
Publication number	US-2016126718-A1
Application number	US-201514875663-A
Country	US
Kind code	A1
Filing date	Oct 5, 2015
Priority date	Oct 31, 2014
Publication date	May 5, 2016
Grant date	—

Abstract

In a semiconductor device, an IGBT and an SJMOSFET connected in parallel have respective gate terminals controlled independently of each other. When a high voltage occurs and a high current flows caused by short-circuit in an external circuit under a condition of ON state of the IGBT and SJMOSFET, an operational amplifier in the control IC detects the overcurrent through the IGBT and controls the gate signal to restrict the current through the IGBT. After that, the operational amplifier throttles the current through the IGBT according to a reference voltage of a capacitor decreasing by the discharge through a constant current source, thus conducting soft-OFF operation of the IGBT.

First claim

What is claimed is:

1 . A semiconductor device comprising:
an insulated gate bipolar transistor (IGBT); a metal oxide semiconductor field effect transistor (MOSFET) formed on a chip on which the IGBT is formed, and exhibiting a withstand voltage lower than that of the IGBT, the MOSFET having a drain and a source connected to a collector and an emitter respectively, of the IGBT; and a control IC delivering a first control signal to a first gate of the IGBT and a second control signal to a second gate of the MOSFET, and comprising an overcurrent detecting circuit for detecting overcurrent in the IGBT and a forcing OFF circuit for forcing the first control signal to be an OFF signal; wherein the forcing OFF circuit of the control IC forces the first control signal to be the OFF signal when the overcurrent detecting circuit detects overcurrent during a time period in which the IGBT and the MOSFET are in an ON state according to the first control signal and the second control signal.

2 . The semiconductor device according to claim 1 , wherein the forcing OFF circuit is a soft-OFF circuit that performs soft-OFF operation of the IGBT receiving the first control signal.

3 . The semiconductor device according to claim 2 , wherein the soft-OFF circuit comprises:
a latch circuit for holding a state of overcurrent detection when the overcurrent detection circuit detects overcurrent of the IGBT; a ramp voltage generating circuit for delivering a ramp voltage with a continuously varying voltage value after the latch circuit has held the state of overcurrent detection; and a soft-OFF control circuit for changing a magnitude of the first control signal toward a turning OFF direction according to the ramp voltage.

4 . The semiconductor device according to claim 2 , wherein the control IC comprises a second overcurrent detecting circuit for detecting overcurrent of the MOSFET and a second forcing OFF circuit for making the second control signal forcedly be an OFF signal, and the second forcing OFF circuit makes the second control signal forcedly be an OFF signal when the second overcurrent detecting circuit detects overcurrent of the MOSFET after the forcing OFF circuit has made the first control signal forcedly be an OFF signal.

5 . The semiconductor device according to claim 1 , wherein the forcing OFF circuit comprises a delay circuit for making the first control signal be an OFF signal after passing a predetermined time period within a time period to guarantee a tolerance to breakdown of the IGBT.

6 . The semiconductor device according to claim 5 , wherein the control IC comprises a second overcurrent detecting circuit for detecting overcurrent of the MOSFET and a second forcing OFF circuit for making the second control signal forcedly be an OFF signal, and the second forcing OFF circuit makes the second control signal forcedly be an OFF signal when the second overcurrent detecting circuit detects overcurrent of the MOSFET after the forcing OFF circuit has made the first control signal forcedly be an OFF signal.

7 . The semiconductor device according to claim 1 , wherein the control IC comprises an overvoltage detecting circuit for detecting overvoltage of a voltage between a collector and an emitter of the IGBT, a second overcurrent detecting circuit for detecting overcurrent in the MOSFET, and a second forcing OFF circuit for making the second control signal forcedly be an OFF signal; and the second forcing OFF circuit makes the second control signal forcedly be an OFF signal when the overvoltage detecting circuit detects overvoltage and the second overcurrent detecting circuit detects overcurrent of the MOSFET after the forcing OFF circuit has made the first control signal forcedly be an OFF signal.

8 . The semiconductor device according to claim 1 , wherein the MOSFET is a super-junction MOSFET.

9 . The semiconductor device according to claim 3 , wherein the control IC comprises a second overcurrent detecting circuit for detecting overcurrent of the MOSFET and a second forcing OFF circuit for making the second control signal forcedly be an OFF signal, and the second forcing OFF circuit makes the second control signal forcedly be an OFF signal when the second overcurrent detecting circuit detects overcurrent of the MOSFET after the forcing OFF circuit has made the first control signal forcedly be an OFF signal.

10 . An apparatus, comprising:
a power semiconductor element; an insulated gate bipolar transistor (IGBT) and a metal oxide semiconductor field effect transistor (MOSFET) on the power semiconductor element, the MOSFET coupled in parallel with the IGBT; and a control device including
an IGBT overcurrent protection device configured to, in response to detecting an overcurrent of the IGBT, generate a first control signal to turn off the IGBT, and
a MOSFET overcurrent protection device configured to, in response to detecting an overcurrent of the MOSFET, generate a second control signal to turn off the MOSFET.

11 . The apparatus of claim 10 , wherein the first control signal is configured to cause a gate voltage of the IGBT to be reduced by a ramping voltage.

12 . The apparatus of claim 10 , wherein the first control signal is configured to be pulled down by turning on of a transistor coupled to a ground potential.

13 . The apparatus of claim 12 , wherein the IGBT overcurrent protection device includes a delay device configured to delay outputting of an overcurrent detection signal to the IGBT by a predetermined period of time.

14 . The apparatus of claim 13 , wherein the predetermined period of time corresponds to a tolerance to breakdown of the IGBT.

Assignees

• Fuji Electric Co Ltd

Inventors

• Naito Tatsuya
• Otsuki Masahito

Classifications

• H02H3/025

  Disconnection after limiting, e.g. when limiting is not sufficient or for facilitating disconnection · CPC title

• H02H3/087 Primary

  for DC applications · CPC title

• H02H3/093

  with timing means {(in general H02H3/027; thermal delay H02H3/085; timing means for undervoltage protection H02H3/247)} · CPC title

• H02H3/10 Primary

  additionally responsive to some other abnormal electrical conditions · CPC title