Multichannel devices with improved performance and methods of making the same

Patent metadata

Field	Value
Publication number	US-2016126340-A1
Application number	US-201414533752-A
Country	US
Kind code	A1
Filing date	Nov 5, 2014
Priority date	Nov 5, 2014
Publication date	May 5, 2016
Grant date	—

Abstract

A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.

First claim

What is claimed is:

1 . A transistor device comprising:
a base structure; a superlattice structure overlying the base structure and comprising a multichannel ridge having sidewalls, the multichannel ridge comprising a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to the other heterostructures of the plurality of heterostructures; and a gate contact that wraps around and substantially surrounds the top and at least one side of the multichannel ridge along at least a portion of its depth.

2 . The transistor of claim 1 , wherein the parameter is a dopant concentration.

3 . The transistor of claim 1 , wherein the parameter is a dopant concentration of each heterostructure, such that longer width channels associated with a given heterostructure are doped with less dopant concentration than shorter width channels associated with a given heterostructure to substantially equalize the pinch-off voltage of each channel of the multichannel ridge during operation.

4 . The transistor of claim 1 , wherein each heterostructure is formed from an AlGaN layer and a GaN layer, wherein the AlGaN layer is the layer that is doped.

5 . The transistor of claim 1 , wherein the parameter is a thickness.

6 . The transistor of claim 1 , wherein the parameter is a thickness, such that each inner heterostructure is formed with a greater thickness than a thickness of at least one of a top heterostructure and a bottom heterostructure.

7 . The transistor of claim 1 , wherein each heterostructure is formed from an AlGaN layer and a GaN layer, wherein the GaN layer of each inner heterostructure is formed with a greater thickness than the GaN layer of at least one of the top and bottom heterostructures.

8 . The transistor of claim 1 , wherein the parameter is a thickness, such that every other inner heterostructure is formed with a greater thickness than a thickness of at least one of a top heterostructure and a bottom heterostructure.

9 . The transistor of claim 8 , wherein each heterostructure is formed from an AlGaN layer and a GaN layer, wherein the GaN layer of every other inner heterostructure is formed with a greater thickness than the GaN layer of at least one of the top and bottom heterostructures.

10 . The transistor of claim 1 , further comprising a plurality of multichannel ridges spaced apart from one another by non-channel openings and comprising a plurality of heterostructures that each form a portion of a parallel channel of the multichannel ridges, wherein a parameter of at least one of the heterostructures for each multichannel ridge is varied to substantially equalize the pinch-off and breakdown voltage of each of the channels of each of the plurality of multichannel ridges.

11 . The transistor of claim 1 , wherein the transistor is a super-lattice castellated gate heterojunction field effect transistor (SLCFET).

12 . A super-lattice castellated gate heterojunction field effect transistor (SLCFET) comprising:
a base structure; a superlattice structure overlying the base structure and comprising a plurality of multichannel ridges having sidewalls and being spaced apart from each other by non-channel openings, the multichannel ridge comprising a plurality of heterostructures that each form a portion of a channel of the SLCFET along with each other parallel heterostructures of the plurality of multichannel ridges, wherein a parameter of at least one of the parallel heterostructures of each of the multichannel ridges is varied; and a gate contact that wraps around and substantially surrounds the top and sides of each the plurality of multichannel ridges along at least a portion of its depth and is interconnected together through the non-channel openings.

13 . The SLCFET of claim 12 , wherein the parameter is a dopant concentration of each heterostructure, such that longer width channels associated with a given heterostructure are doped with less dopant concentration than shorter width channels associated with a given heterostructure for each of the plurality of heterostructures to substantially equalize the pinch-off voltage of each channel of the SLCFET during operation.

14 . The SLCFET of claim 13 , wherein each heterostructure is formed from an AlGaN layer and a GaN layer, wherein the AlGaN layer is the layer that is doped for each of the heterostructures for each of the multichannel ridges.

15 . The SLCFET of claim 12 , wherein the parameter is a thickness, such that each inner heterostructure is formed with a greater thickness than a thickness of at least one of a top heterostructure and a bottom heterostructure for each of the multichannel ridges.

16 . The SLCFET of claim 15 , wherein each heterostructure is formed from an AlGaN layer and a GaN layer, wherein the GaN layer of each inner heterostructure is formed with a greater thickness than the GaN layer of the at least one of top and bottom heterostructures for each of the multichannel ridges.

17 . The SLCFET of claim 12 , wherein the parameter is a thickness, such that every other inner heterostructure is formed with a greater thickness than a thickness of at least one of a top heterostructure and a bottom heterostructure.

18 . The transistor of claim 17 , wherein each heterostructure is formed from an AlGaN layer and a GaN layer, wherein the GaN layer of every other inner heterostructure is formed with a greater thickness than the GaN layer of at least one of the top and bottom heterostructures.

19 . A method of forming a transistor device, the method comprising:
forming a superlattice structure comprising a plurality of heterostructures over a base structure by sequentially depositing each layer of a plurality heterostructures over the base structure with one layer of each heterostructure being doped; etching away openings in the superlattice structure over a channel region to form a castellated region in the channel region of alternating multichannel ridges with edges and non-channel openings, wherein a parameter of at least one of corresponding parallel heterostructures of each of the multichannel ridges is varied; and performing a gate contact fill process to form a gate contact that wraps around and substantially surrounds the top and sides of each the plurality of multichannel ridges along at least a portion of its depth and connects each one of the alternating multichannel bridges to one another through the non-channel openings.

20 . The method of claim 19 , wherein the parameter is a dopant concentration.

21 . The method of claim 19 , wherein the parameter is a dopant concentration for each heterostructure, such that longer width channels associated with a given heterostructure are doped with less dopant concentration than shorter width channels associated with a given heterostructure for each of the plurality of heterostructures to substantially equalize the pinch-off voltage of each channel of the SLCFET during operation.

22 . The method of claim 19 , wherein the parameter is a thickness.

23 . The method of claim 19 , wherein the parameter is a thickness, such that each inner heterostructure is formed with a greater thickness than a thickness of at least one of a top heterostructure and a bottom heterostructure for each of the multichannel ridges.

24 . The method of claim 19 , wherein the parameter is a thickness, such that every oth

Assignees

• Nechay Bettina A
• Gupta Shalini
• King Matthew Russell
• Stewart Eric J
• Howell Robert S
• Parke Justin Andrew
• Cramer Harlan Carl
• Henry Howell George
• Freitag Ronald G
• Renaldo Karen Marie
• Northrop Grumman Systems Corp

Inventors

• Nechay Bettina A
• Gupta Shalini
• King Matthew Russell
• Stewart Eric J
• Howell Robert S
• Parke Justin Andrew
• Cramer Harlan Carl
• Henry Howell George
• Freitag Ronald G
• Renaldo Karen Marie

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H10D62/117

  Shapes of semiconductor bodies · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D62/8171

  Doping structures, e.g. doping superlattices or nipi superlattices · CPC title

• H10D62/824

  comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title