Cmos image sensor with enhanced dynamic range

Patent metadata

Field	Value
Publication number	US-2016126282-A1
Application number	US-201414552501-A
Country	US
Kind code	A1
Filing date	Nov 25, 2014
Priority date	Oct 31, 2014
Publication date	May 5, 2016
Grant date	—

Abstract

An image sensor includes a semiconductor substrate having a main surface, a transfer transistor having a transfer gate disposed on the main surface, a light-sensing structure on one side of the transfer gate, a floating diffusion node on the other side of the transfer gate, a reset transistor serially connected to the transfer transistor via the floating diffusion node, a source-follower transistor having a source-follower gate, and a vertical capacitor having a first vertical electrode plate and a second vertical electrode plate. The first vertical electrode plate is electrically connected to the source-follower gate and the floating diffusion node.

First claim

1 . An image sensor, comprising:
a semiconductor substrate having a main surface; a transfer transistor having a transfer gate disposed on the main surface of the semiconductor substrate; a light-sensing structure disposed on one side of the transfer gate in the semiconductor substrate; a floating diffusion node on the other side of the transfer gate in the semiconductor substrate; a reset transistor serially connected to the transfer transistor through the floating diffusion node; a source-follower transistor comprising a source-follower gate; and a vertical capacitor structure having a first vertical electrode plate and a second vertical electrode plate, wherein the first vertical electrode plate is electrically coupled to the source-follower gate and the floating diffusion node.

2 . The image sensor according to claim 1 , wherein the source-follower gate is electrically coupled to the floating diffusion node through a first conductive plug, a first metal interconnection, and a second conductive plug.

3 . The image sensor according to claim 2 , wherein the first conductive plug and the second conductive plug are disposed in a same dielectric layer.

4 . The image sensor according to claim 2 , wherein the source-follower gate is electrically coupled to the first vertical electrode plate of the vertical capacitor structure through a second metal interconnection.

5 . The image sensor according to claim 1 , wherein the first vertical electrode plate and the second vertical electrode plate are interdigitated.

6 . The image sensor according to claim 1 , wherein the first vertical electrode plate and the second vertical electrode plate are disposed vertical to the main surface of the semiconductor substrate.

7 . The image sensor according to claim 1 further comprising a readout transistor serially connected to the source-follower transistor through a commonly used doping region.

8 . The image sensor according to claim 7 , wherein the transfer transistor and the reset transistor are disposed on a first active region, and the source-follower transistor and the readout transistor are disposed on a second active region, wherein the first active region is isolated from the second active region by a shallow trench isolation (STI) structure.

9 . The image sensor according to claim 1 , wherein the light-sensing structure is a photodiode comprising a P + surface doping region and an N − doping region, which constitute a pinned photodiode in the semiconductor substrate.

10 . The image sensor according to claim 1 , wherein the first vertical electrode plate and the second vertical electrode plate are composed of a stack of a first metal layer, a trench-type via plug, and a second metal layer.

11 . The image sensor according to claim 10 further comprising a dielectric layer disposed between the first vertical electrode plate and the second vertical electrode plate, and a capacitance is formed between the trench-type via plugs of the first vertical electrode plate and the second vertical electrode plate.

12 . The image sensor according to claim 1 , wherein the second vertical electrode plate is coupled to a bias voltage when in operation.

13 . The image sensor according to claim 12 , wherein the bias voltage is ground.

Assignees

• Powerchip Technology Corp

Inventors

• Chen Min-Hui
• Chung Chih-Ping
• Ho Ming-Yu

Classifications

• H10F39/8037

  the integrated elements comprising a transistor · CPC title

• H10F39/8033

  Photosensitive area · CPC title

• H10F39/807

  Pixel isolation structures · CPC title

• H10F39/802

  Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes · CPC title

• H10F39/18 Primary

  Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors · CPC title