Metal-assisted chemical etching of a semiconductive substrate with high aspect ratio, high geometic uniformity, and controlled 3d profiles

Patent metadata

Field	Value
Publication number	US-2016126133-A1
Application number	US-201514930161-A
Country	US
Kind code	A1
Filing date	Nov 2, 2015
Priority date	Nov 4, 2014
Publication date	May 5, 2016
Grant date	—

Abstract

An embodiment of a method for metal-assisted chemical etching of a semiconductive substrate comprises forming a patterned coating on a top surface of a substrate layer of a silicon wafer; applying a noble metal layer over the patterned coating such that a portion of the noble metal layer is in contact with the top surface of the substrate layer; and immersing the silicon wafer in a wet etching solution to form a trench under the portion of the noble metal layer that is contact with the top surface of the substrate layer. Further, the trench may be filled with copper material to form a through silicon via structure. Such embodiments provide etching techniques that enable etched formations that are deep (e.g., high-aspect-ratio) and uniform as opposed to shallow etchings (i.e., low-aspect-ratio) or non-uniform deep etchings.

First claim

Therefore, at least the following is claimed:

1 . A method for forming semiconductor structures comprising:
forming a patterned coating on a top surface of a substrate layer of a silicon wafer; applying a noble metal layer over the patterned coating such that a portion of the noble metal layer is in contact with the top surface of the substrate layer; and immersing the silicon wafer in a wet etching solution to form a trench under the portion of the noble metal layer that is contact with the top surface of the substrate layer, wherein an etching profile of the trench is rationally determined by controlling at least one of a thickness of the noble metal layer, a morphology of the noble metal layer, or a composition of the wet etching solution.

2 . The method of claim 1 , further comprising filling the trench with copper material to form a through silicon via structure.

3 . The method of claim 1 , wherein the noble metal layer comprises a layer of gold.

4 . The method of claim 1 , further comprising controlling surface properties of the substrate before preparation of the noble metal layer in order to control the morphology of the noble metal layer.

5 . The method of claim 1 , wherein the noble metal layer is applied via DC sputtering.

6 . The method of claim 1 , wherein a thickness of the noble metal layer is substantially uniform over the silicon wafer, wherein a diameter of the silicon wafer is at least 4 inches.

7 . The method of claim 1 , wherein the wet etching solution comprises a solution of H 2 O 2 and HF.

8 . The method of claim 7 , wherein the wet etching solution further comprises ethanol.

9 . The method of claim 1 , wherein the etching profile of the trench is further rationally determined by controlling a temperature of the wet etching solution.

10 . The method of claim 1 , further comprising stirring the wet etching solution during immersion of the silicon wafer.

11 . The method of claim 1 , wherein the trench is substantially vertical.

12 . The method of claim 1 , wherein the trench is slanted.

13 . The method of claim 1 , wherein sidewalls of the trench are substantially tapered.

14 . A method for controlling excessive etching in forming semiconductor structures comprising:
forming a patterned coating on a top surface of a substrate layer of a silicon wafer; applying a noble metal layer over the patterned coating such that a portion of the noble metal layer is in contact with the top surface of the substrate layer of the silicon wafer; cutting the silicon wafer into a plurality of chips; applying a negative voltage bias to one or more of the plurality of chips; and immersing the one or more of the plurality of chips having the negative voltage bias in a wet etching solution to form a trench under the portion of the noble metal layer that is contact with the top surface of the substrate layer.

15 . The method of claim 14 , wherein the noble metal layer is applied via DC sputtering.

16 . The method of claim 14 , further comprising filling the trench with copper material to form a through silicon via structure.

17 . The method of claim 14 , wherein the wet etching solution comprises a solution of H 2 O 2 and HF.

18 . The method of claim 14 , further comprising stirring the wet etching solution during immersion of the silicon wafer.

19 . The method of claim 14 , wherein the trench is substantially vertical.

20 . The method of claim 14 , further comprising increasing the negative voltage bias to increase a depth of the trench or to increase a sidewall angle of the trench.

Assignees

• Georgia Tech Res Inst

Inventors

• Li Liyi
• Wong Ching Ping
• Moon Jack K
• Zhao Xueying

Classifications

• H10W20/2125

  Top-view shapes · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10P72/0426

  with the semiconductor substrates being dipped in baths or vessels · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10P50/642

  Chemical etching · CPC title