Feature amount conversion apparatus, learning apparatus, recognition apparatus, and feature amount conversion program product

Patent metadata

Field	Value
Publication number	US-2016125271-A1
Application number	US-201414895198-A
Country	US
Kind code	A1
Filing date	May 28, 2014
Priority date	Jun 3, 2013
Publication date	May 5, 2016
Grant date	—

Abstract

A feature amount conversion apparatus includes a plurality of bit rearrangement units, a plurality of logical operation units, and a feature integration unit. The bit rearrangement units generate rearranged bit strings by rearranging elements of an inputted binary feature vector into diverse arrangements. The logical operation units generate logically-operated bit strings by performing a logical operation on the inputted feature vector and each of the rearranged bit strings. The feature integration unit generates a nonlinearly converted feature vector by integrating the generated logically-operated bit strings.

First claim

1 . A feature amount conversion apparatus comprising:
a bit rearrangement portion that generates a plurality of rearranged bit strings by rearranging elements of an inputted feature vector being binary into diverse arrangements; a logical operation portion that generates a plurality of logically-operated bit strings by performing a logical operation on the inputted feature vector and each of the rearranged bit strings; and a feature integration portion that generates a nonlinearly converted feature vector by integrating the generated logically-operated bit strings.

2 . The feature amount conversion apparatus according to claim 1 , wherein
the feature integration portion further integrates the elements of the inputted feature vector as well as the generated logically-operated bit strings.

3 . The feature amount conversion apparatus according to claim 1 , wherein
the logical operation portion calculate the exclusive OR of the rearranged bit strings and the inputted feature vector.

4 . The feature amount conversion apparatus according to claim 1 , wherein
the bit rearrangement portion generates the rearranged bit strings by performing a rotate shift operation with no carry on the elements of the inputted feature vector.

5 . The feature amount conversion apparatus according to claim 4 , wherein
when the inputted feature vector is d-dimensional, d/2 bit rearrangement portions are provided.

6 . The feature amount conversion apparatus according to claim 1 , wherein
the bit rearrangement portion randomly rearranges the elements of the inputted feature vector.

7 . The feature amount conversion apparatus according to claim 1 , further comprising:
a plurality of binarization portions, each generating the feature vector being binary by binarizing an inputted real number feature vector; and a plurality of co-occurring element generation portions respectively corresponding to the plurality of binarization portions, wherein each of the co-occurring element generation portions includes the plurality of the bit rearrangement portions and the plurality of the logical operation portions; the feature vector of the binary value is inputted to the plurality of co-occurring element generation portions respectively from the plurality of corresponding binarization portions; the feature integration portion generates the nonlinearly converted feature vector by integrating all the logically-operated bit strings generated respectively by the plurality of the logical operation portions in each of the co-occurring element generation portions.

8 . The feature amount conversion apparatus according to claim 1 , wherein
the feature vector being binary is acquired by binarizing a histograms of oriented gradients feature amount.

9 . A feature amount conversion apparatus comprising:
a bit rearrangement portion that generates a rearranged bit string by rearranging elements of an inputted feature vector being binary; a logical operation portion that generates a logically-operated bit string by performing a logical operation on the inputted feature vector and the rearranged bit string; and a feature integration portion that generates a nonlinearly converted feature vector by integrating the elements of the feature vector and the generated logically-operated bit string.

10 . A feature amount conversion apparatus comprising:
a plurality of bit rearrangement portions that generate a rearranged bit string by rearranging elements of an inputted feature vector being binary into diverse arrangements; a logical operation portion that generates logically-operated bit strings by performing a logical operation on the rearranged bit strings generated by the bit rearrangement portions; and a feature integration portion that generates a nonlinearly converted feature vector by integrating the elements of the feature vector and the generated logically-operated bit strings.

11 . A feature amount conversion apparatus comprising:
a plurality of bit rearrangement portions that generate a rearranged bit string by rearranging elements of an inputted feature vector being binary into diverse arrangements; a plurality of logical operation portions that generate logically-operated bit strings by performing a logical operation on the rearranged bit strings generated by the bit rearrangement portions; and a feature integration portion that generates a nonlinearly converted feature vector by integrating the generated logically-operated bit strings.

12 . A learning apparatus comprising:
a feature amount conversion apparatus according to claim 1 ; and a learning portion that achieves learning by using the nonlinearly converted feature vector generated by the feature amount conversion apparatus.

13 . A recognition apparatus comprising:
a feature amount conversion apparatus according to claim 1 , and a recognition portion that achieves recognition by using the nonlinearly converted feature vector generated by the feature amount conversion apparatus.

14 . The recognition apparatus according to claim 13 , wherein
the recognition portion
calculates the inner product of a weight vector in the recognition and the nonlinearly converted feature vector in the order of the largest distribution to the smallest or in the order of the highest entropy value to the lowest, and
terminates the calculation of the inner product when the inner product is determined to be greater or smaller than a predetermined threshold value for recognition.

15 . A feature amount conversion program product stored in a non-transitory computer-readable medium, the program product including instructions causing a computer to function as a plurality of bit rearrangement portions, as a plurality of logical operation portions, and as a feature integration portion,
the bit rearrangement portions generating a rearranged bit string by rearranging elements of an inputted feature vector being binary into diverse arrangements, the logical operation portions generating logically-operated bit strings by performing a logical operation on the inputted feature vector and each of the rearranged bit strings, the feature integration portion generating a nonlinearly converted feature vector by integrating the generated logically-operated bit strings.

Assignees

• Denso Corp

Inventors

• Ambai Mitsuru
• Shimizu Mikio

Classifications

• H03M7/14 Primary

  Conversion to or from non-weighted codes · CPC title

• G06F18/217

  Validation; Performance evaluation; Active pattern learning techniques · CPC title

• G06T7/60

  Analysis of geometric attributes · CPC title

• G06T2207/20081

  Training; Learning · CPC title

• G06T2200/28

  involving image processing hardware · CPC title