Low quiescent current voltage regulator with high load-current capability

Patent metadata

Field	Value
Publication number	US-2016124454-A1
Application number	US-201414533555-A
Country	US
Kind code	A1
Filing date	Nov 5, 2014
Priority date	Nov 5, 2014
Publication date	May 5, 2016
Grant date	—

Abstract

Embodiments of voltage regulators and methods for operating a voltage regulator are described. In one embodiment, a voltage regulator includes a set of current mirror circuits configured to convert an input voltage into an output voltage and a voltage buffer circuit configured to buffer a reference voltage for the set of current mirror circuits. The set of current mirror circuits form a positive feedback loop. Other embodiments are also described.

First claim

What is claimed is:

1 . A voltage regulator, the voltage regulator comprising:
a set of current mirror circuits configured to convert an input voltage into an output voltage, wherein the set of current mirror circuits form a positive feedback loop; and a voltage buffer circuit configured to buffer a reference voltage for the set of current mirror circuits.

2 . The voltage regulator of claim 1 , wherein the positive feedback loop has a loop gain that is less than 1.

3 . The voltage regulator of claim 1 , wherein the output voltage is lower than the input voltage.

4 . The voltage regulator of claim 1 , wherein the input and output voltages are direct current (DC) voltages.

5 . The voltage regulator of claim 1 , wherein the set of current mirror circuits comprises a first current mirror circuit and a second current mirror circuit, wherein an input terminal of the first current mirror circuit is connected to an output terminal of the second current mirror and an output terminal of the first current mirror circuit is connected to an input terminal of the second current mirror circuit.

6 . The voltage regulator of claim 5 , wherein the first current mirror circuit comprises a first PMOS transistor and a second PMOS transistor, and wherein the second current mirror circuit comprises a first NMOS transistor and a second NMOS transistor.

7 . The voltage regulator of claim 5 , wherein gate terminals of the first and second PMOS transistors are connected to each other, and wherein the gate terminal of the second PMOS transistor is connected to a drain terminal of the second PMOS transistor.

8 . The voltage regulator of claim 7 , wherein gate terminals of the first and second NMOS transistors are connected to each other, and wherein the gate terminal of the second NMOS transistor is connected to a drain terminal of the second NMOS transistor.

9 . The voltage regulator of claim 8 , wherein a drain terminal of the first PMOS transistor is connected to a drain terminal of the first NMOS transistor, and wherein the drain terminal of the second PMOS transistor is connected to the drain terminal of the second NMOS transistor.

10 . The voltage regulator of claim 1 , wherein the voltage buffer circuit comprises a source follower transistor connected between the reference voltage and the set of current mirror circuits.

11 . The voltage regulator of claim 1 , wherein the reference voltage is lower than the input voltage and the output voltage.

12 . The voltage regulator of claim 1 , further comprising a startup circuit configured to generate a startup current for the set of current mirror circuits.

13 . The voltage regulator of claim 12 , wherein the startup circuit comprises a resistor connected to an input terminal, from which the input voltage is input into the voltage regulator, and to the set of current mirror circuits.

14 . The voltage regulator of claim 1 , further comprising a resistor connected to an output terminal, from which the output voltage is output from the voltage regulator, and to the set of current mirror circuits.

15 . The voltage regulator of claim 1 , wherein the input voltage is around 3.3V and the output voltage is around 1.8V.

16 . A voltage regulator, the voltage regulator comprising:
a set of current mirror circuits configured to convert an input direct current (DC) voltage into an output DC voltage, wherein the set of current mirror circuits form a positive feedback loop having a loop gain that is less than 1, and wherein the output voltage is lower than the input voltage; and a voltage buffer circuit configured to buffer a reference DC voltage for the set of current mirror circuits.

17 . The voltage regulator of claim 16 , wherein the set of current mirror circuits comprises a first current mirror circuit and a second current mirror circuit, wherein the first current mirror circuit comprises a first PMOS transistor and a second PMOS transistor, wherein the second current mirror circuit comprises a first NMOS transistor and a second NMOS transistor, wherein gate terminals of the first and second PMOS transistors are connected to each other, wherein the gate terminal of the second PMOS transistor is connected to a drain terminal of the second PMOS transistor, wherein gate terminals of the first and second NMOS transistors are connected to each other, wherein the gate terminal of the second NMOS transistor is connected to a drain terminal of the second NMOS transistor, wherein a drain terminal of the first PMOS transistor is connected to a drain terminal of the first NMOS transistor, and wherein the drain terminal of the second PMOS transistor is connected to the drain terminal of the second NMOS transistor.

18 . The voltage regulator of claim 17 , further comprising a startup circuit configured to generate a startup current for the set of current mirror circuits, and wherein the startup circuit comprises a resistor connected to an input terminal, from which the input voltage is input into the voltage regulator, and to the set of current mirror circuits.

19 . The voltage regulator of claim 17 , wherein the input voltage is around 3.3V and the output voltage is around 1.8V.

20 . A method for operating a voltage regulator, the method comprising:
buffering a reference voltage for a set of current mirror circuits; and converting an input voltage into an output voltage using the set of current mirror circuits, wherein the set of current mirror circuits form a positive feedback loop; and

Assignees

• Nxp Bv

Inventors

• Chellappa Ananthasayanam

Classifications

• G05F3/26

  Current mirrors · CPC title

• G05F3/242

  with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage · CPC title

• G05F1/56

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title

• G05F3/262 Primary

  using field-effect transistors only · CPC title