Display panel and thin film transistor array substrate included in the same

Patent metadata

Field	Value
Publication number	US-2016124254-A1
Application number	US-201514700984-A
Country	US
Kind code	A1
Filing date	Apr 30, 2015
Priority date	Nov 5, 2014
Publication date	May 5, 2016
Grant date	—

Abstract

Provided are a display panel and a thin film transistor array substrate. According to one or more exemplary embodiments, a display panel includes: a first substrate including a pixel area and a non-pixel area; a second substrate that faces the first substrate; and a crack guide groove disposed on a surface of at least one of the first substrate and the second substrate.

First claim

What is claimed is:

1 . A display panel comprising:
a first substrate comprising a pixel area and a non-pixel area; a second substrate that faces the first substrate; and a crack guide groove disposed on a surface of at least one of the first substrate and the second substrate.

2 . The display panel of claim 1 , wherein the crack guide groove has at least one of a solid line shape and a dotted line shape along a first direction.

3 . The display panel of claim 1 , wherein crack guide groove portions are disposed in opposite edge portions of the at least one of the first substrate and the second substrate,
wherein a first crack guide groove portion and a second crack guide groove portion of the crack guide groove are disposed in the opposite edge portions, respectively, and wherein the first crack guide groove portion and the second crack guide groove portion are separated in a first direction and substantially aligned relative to a second direction substantially perpendicular to the first direction.

4 . The display panel of claim 1 , wherein a depth of the crack guide groove is equal to or smaller than one tenth of a thickness of the at least one of the first substrate and the second substrate.

5 . The display panel of claim 1 , wherein a cross section shape of the crack guide groove is selected from a group consisting of a triangle and a rectangle.

6 . The display panel of claim 1 , wherein the first substrate and the second substrate are substantially flat and the at least one of the first substrate and the second substrate is configured to generate a crack along the crack guide groove when bent more than a threshold bending degree.

7 . The display panel of claim 1 , wherein the first substrate includes an inner surface that faces the second substrate and an outer surface that is an opposite surface of the inner surface of the first substrate,
the second substrate includes an inner surface that faces the inner surface of the first substrate and an outer surface that is an opposite surface of the inner surface of the second substrate, and the crack guide groove is disposed on at least one of the inner surface of the first substrate, the outer surface of the first substrate, the inner surface of the second substrate, and the outer surface of the second substrate.

8 . The display panel of claim 1 , wherein the crack guide groove extends along a first direction on the surface of the at least one of the first substrate and the second substrate, and
wherein the crack guide groove is disposed on the center of the at least one of the first substrate and the second substrate with respect to a direction substantially perpendicular to the first direction.

9 . The display panel of claim 1 , further comprising one or more additional crack guide grooves disposed along a first direction on the surface of the at least one of the first substrate and the second substrate, wherein the crack guide grooves are spaced apart from each other along a second direction substantially perpendicular to the first direction.

10 . The display panel of claim 1 , further comprising:
a liquid crystal layer interposed between the first substrate and the second substrate; and a black matrix arranged in an area corresponding to the non-pixel area, wherein the crack guide groove overlaps a part of the black matrix.

11 . The display panel of claim 1 , further comprising:
a light emitting layer disposed between the first substrate and the second substrate, the light emitting layer disposed in an area corresponding to the pixel area; and a pixel-defining layer disposed in an area corresponding to the non-pixel area, wherein the crack guide groove overlaps a part of the pixel-defining layer.

12 . A thin film transistor array substrate comprising:
a substrate comprising a pixel area and a non-pixel area; a thin film transistor disposed on the substrate; a first electrode disposed on the substrate in an area corresponding to the pixel area, the first electrode being electrically connected to the thin film transistor; and at least one crack guide groove disposed on a surface of the substrate.

13 . The thin film transistor array substrate of claim 12 , wherein the crack guide groove has at least one of a solid line shape and a dotted line shape along a first direction.

14 . The thin film transistor array substrate of claim 12 , wherein crack guide groove portions are disposed in opposite edge portions of the substrate,
wherein a first crack guide groove portion and a second crack guide groove portion of the crack guide groove have solid line shapes and are disposed in the opposite edge portions, respectively, and wherein the first crack guide groove portion and the second crack guide groove portion are separated in a first direction and substantially aligned relative to a second direction substantially perpendicular to the first direction.

15 . The thin film transistor array substrate of claim 12 , wherein a depth of the crack guide groove is equal to or smaller than one tenth of a thickness of the substrate.

16 . The thin film transistor array substrate of claim 12 , wherein the substrate is substantially flat and configured to generate a crack along the crack guide groove when the substrate bends more than a threshold bending degree.

17 . The thin film transistor array substrate of claim 12 , wherein the crack guide groove extends along a first direction on the surface of the substrate, and
wherein the crack guide groove is disposed on the center portion of the substrate with respect to a second direction substantially perpendicular to the first direction.

18 . The thin film transistor array substrate of claim 12 , wherein one or more additional crack guide grooves are disposed along a first direction on the surface of the substrate, and
wherein the crack guide grooves are spaced apart from each other along a second direction perpendicular to the first direction.

19 . The thin film transistor array substrate of claim 12 , further comprising:
a black matrix arranged in an area corresponding to the non-pixel area, wherein the crack guide groove overlaps a part of the black matrix.

20 . The thin film transistor array substrate of claim 12 , further comprising:
a light emitting layer dispose din an area corresponding to the pixel area; and a pixel-defining layer disposed in an area corresponding to the non-pixel area, wherein the crack guide groove overlaps a part of the pixel-defining layer.

Assignees

• Samsung Display Co Ltd

Inventors

• Yoon Won Gap
• Jang Ji Eun
• Tak Kyung-Seon
• Oh Keun Chan

Classifications

• H10D30/67

  Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} · CPC title

• H10D86/411

  characterised by materials, geometry or structure of the substrates · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H01L27/1218

  Electricity · mapped topic

• G02F1/133512 Primary

  Light shielding layers, e.g. black matrix (G02F1/136209 takes precedence) · CPC title